Kannanthodath V. Jayakumar

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Linear prediction to suppress spurs in a digital phase-locked loop
- Patent number 12,191,866
- Issue date Jan 7, 2025
- Kannanthodath V. Jayakumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Modified control loop in a digital phase-locked loop
- Patent number 12,166,494
- Issue date Dec 10, 2024
- Kannanthodath V. Jayakumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Jitter self-test using timestamps
- Patent number 11,764,913
- Issue date Sep 19, 2023
- Skyworks Solutions, Inc.
- Raghunandan K. Ranganathan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Jitter self-test using timestamps
- Patent number 11,228,403
- Issue date Jan 18, 2022
- Skyworks Solutions, Inc.
- Raghunandan K. Ranganathan
- G01 - MEASURING TESTING
Information Patent Grant
On-chip phase-locked loop response measurement
- Patent number 11,018,679
- Issue date May 25, 2021
- Silicon Laboratories Inc.
- Kannanthodath V. Jayakumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Accurate and reliable digital PLL lock indicator
- Patent number 10,819,354
- Issue date Oct 27, 2020
- Silicon Laboratories Inc.
- Kannanthodath V. Jayakumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Relative frequency offset error and phase error detection for clocks
- Patent number 10,608,649
- Issue date Mar 31, 2020
- Silicon Laboratories Inc.
- Kannanthodath V. Jayakumar
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
MODIFIED CONTROL LOOP IN A DIGITAL PHASE-LOCKED LOOP
- Publication number 20230198531
- Publication date Jun 22, 2023
- Skyworks Solutions, Inc.
- Kannanthodath V. Jayakumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LINEAR PREDICTION TO SUPPRESS SPURS IN A DIGITAL PHASE-LOCKED LOOP
- Publication number 20230094645
- Publication date Mar 30, 2023
- Skyworks Solutions, Inc.
- Kannanthodath V. Jayakumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
JITTER SELF-TEST USING TIMESTAMPS
- Publication number 20220123877
- Publication date Apr 21, 2022
- Skyworks Solutions, Inc.
- Raghunandan K. Ranganathan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
JITTER SELF-TEST USING TIMESTAMPS
- Publication number 20210176020
- Publication date Jun 10, 2021
- Silicon Laboratories Inc.
- Raghunandan K. Ranganathan
- G01 - MEASURING TESTING
Information Patent Application
ON-CHIP PHASE-LOCKED LOOP RESPONSE MEASUREMENT
- Publication number 20210159904
- Publication date May 27, 2021
- Silicon Laboratories Inc.
- Kannanthodath V. Jayakumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ACCURATE AND RELIABLE DIGITAL PLL LOCK INDICATOR
- Publication number 20200162081
- Publication date May 21, 2020
- Silicon Laboratories Inc.
- Kannanthodath V. Jayakumar
- H03 - BASIC ELECTRONIC CIRCUITRY

Kannanthodath V. Jayakumar

Person

Patents Grantslast 30 patents

Linear prediction to suppress spurs in a digital phase-locked loop

Modified control loop in a digital phase-locked loop

Jitter self-test using timestamps

Jitter self-test using timestamps

On-chip phase-locked loop response measurement

Accurate and reliable digital PLL lock indicator

Relative frequency offset error and phase error detection for clocks

Patents Applicationslast 30 patents

MODIFIED CONTROL LOOP IN A DIGITAL PHASE-LOCKED LOOP

LINEAR PREDICTION TO SUPPRESS SPURS IN A DIGITAL PHASE-LOCKED LOOP

JITTER SELF-TEST USING TIMESTAMPS

JITTER SELF-TEST USING TIMESTAMPS

ON-CHIP PHASE-LOCKED LOOP RESPONSE MEASUREMENT

ACCURATE AND RELIABLE DIGITAL PLL LOCK INDICATOR