This disclosure is related to integrated circuits and more particularly to clock generator integrated circuits.
In general, jitter is unwanted deviation from true periodicity of a presumably periodic signal, e.g., a clock signal. Random jitter is caused by thermal noise in electrical circuits and is unpredictable, may be the composite of many uncorrelated noise sources, and typically follows a normal distribution. The amount of tolerable jitter varies with the target application. In an exemplary application, e.g., clock and data recovery circuits for digital communications, jitter of a sampling clock signal determines the performance of the digital communications system and as the frequency of the sampling clock signal increases, tolerance for jitter decreases. High performance phase-locked loops are used in clock generators as jitter attenuators to achieve a sampling clock signal with jitter of less than 100 femto-seconds root-mean-square (RMS) over 12 kHz to 20 MHz. However, individual integrated circuits vary and production testing is used to identify any integrated circuit products with jitter that exceeds a target specification.
Referring to
In at least one embodiment, an integrated circuit for estimating jitter of a clock signal includes a clock generator circuit configured to generate a phase-adjusted clock signal based on an input clock signal and a feedback clock signal using a frequency divider circuit. The integrated circuit includes a time-to-digital converter circuit configured to generate digital time codes corresponding to first edges of the clock signal using a reference clock signal. The integrated circuit includes a control circuit configured to cause the time-to-digital converter circuit to generate N digital time codes for each phase adjustment of P phase adjustments applied to the clock generator circuit. P is a first integer greater than zero and N is a second integer greater than zero. The integrated circuit includes a logic circuit configured to generate a jitter indicator based on an expected period of the clock signal and the N digital time codes for each phase adjustment of the P phase adjustments.
In at least one embodiment, a method for estimating jitter of a clock signal includes generating a phase-adjusted clock signal based on an input clock signal and a feedback clock signal using a frequency-divided clock signal. The method generating N digital time codes for each phase adjustment of P phase adjustments of the phase-adjusted clock signal using a reference clock signal. Each digital time code of the N digital time codes corresponds to a first edge of a clock signal based on the frequency-divided clock signal. P is a first integer greater than zero and N is a second integer greater than zero. The method includes generating a jitter indicator based on an expected period of the clock signal and the N digital time codes for each phase adjustment of the P phase adjustments.
The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.
The use of the same reference symbols in different drawings indicates similar or identical items.
A jitter self-testing technique uses circuits included in an integrated circuit product to estimate jitter of a clock signal of the integrated circuit product. The technique provides high-resolution jitter estimates (e.g., jitter estimates in ranges less than one picosecond) using negligible testing time (e.g., 100 ms for a 10 MHz clock signal) and reduces or eliminates the need for expensive testing equipment. Referring to
Referring to
where xi is a digital code corresponding to the observed occurrence of the ith clock edge and
Referring to
By introducing a phase adjustment, incrementing the phase adjustment P times, and generating a statistically significant number N of digital codes for each phase adjustment of the P phase adjustments, jitter self-test circuit 204 estimates the RMS jitter of a clock-signal-under-test. Referring to
In at least one embodiment of jitter self-test circuit 704, select circuits 711 and 712 provide flexibility to operate jitter self-test circuit 704 in various modes to test different clock signals of integrated circuit product 700. For example, jitter self-test circuit 704 is selectively configurable in a first mode with clock signal CLK_FB as the clock-signal-under-test CLK_TEST and reference clock signal CLK_REF as the reference clock signal CLK_REF_TDC. Jitter self-test circuit 704 is selectively configurable in a second mode with reference clock signal CLK_REF as the clock-signal-under-test CLK_TEST and clock signal CLK_FB as reference clock signal CLK_REF_TDC. The first mode assumes that reference clock signal CLK_REF is an ideal clock signal to estimate jitter of a clock signal (e.g., clock signal CLK_FB) derived from clock signal CLK_VCO by clock generator 702. The second mode uses a clock derived from clocks signal CLK_VCO as reference clock signal CLK_REF_TDC to estimate jitter on reference clock signal CLK_REF received by integrated circuit product 700. In other embodiments of jitter self-test circuit 704, time-to-digital converter 726 is directly coupled to receive clock signal CLK_IN as the clock-signal-under-test and use clock signal CLK_FB as reference clock signal CLK_REF_TDC.
In at least one embodiment, control circuit 706 sweeps the phase by causing frequency divider 718, frequency divider 720, or frequency divider 722 to apply phase adjustment ΔT. Memory 724 stores a stream of digital time codes for use by digital processing circuit 708. Digital processing circuit 708 includes circuitry that estimates mean period information TPER. In at least one embodiment, a moving average filter estimates mean period information TPER, as illustrated in
where N is the number of points being averaged and M is the order of the moving average filter. In at least one embodiment, the averaging length is programmable. In some embodiments, rather than determine mean period information, a mean period value TPER can be received from a user and stored in memory 724. Digital processing circuit 708 includes custom circuits or a digital signal processor that executes instructions stored in memory 724 to determine mean period value TPER and estimate the standard deviation (σ) of the distribution of clock edges based on N digital time codes for each phase adjustment of P phase adjustments. For example, digital processing circuit 708 associates each of the N digital time codes with a first set of digital time codes or a second set of digital codes by comparing, for each phase adjustment of P phase adjustments, each digital time code Ti of the N digital time codes to an initial digital time code T0. If the difference between two successive digital time codes is less than or equal to the estimated period, i.e., Ti==T0+i×TPER, then the digital code is associated with the first set. Alternately, if the difference between two successive digital time codes is greater than to the estimated period, i.e., Ti≠T0+i×TPER, then the digital code is associated with the second set. Digital processing circuit 708 provides the standard deviation of the first or second set of digital time codes or a function of the standard deviation of the first or second set of digital time codes to a terminal of integrated circuit product 700 or stores the standard deviation or function of the standard deviation for later access by a user.
Referring to
Referring to
Jitter self-test circuit 704 captures timestamps generated by time-to-digital converter 726 for N cycles (e.g., 1000 cycles) of clock-signal-under-test CLK_TEST (1006). After capturing N timestamps, digital processing circuit 708 associates each timestamp with a first set of timestamps or a second set of timestamps by comparing each timestamp of the N timestamps to a value based on index i and the initial timestamp T0. If Ti==T0+i×TPER, then the timestamp is associated with the first set. If Ti≠T0+i×TPER, then digital processing circuit 708 associates the timestamp with the second set. Then, control circuit 706 increments the applied phase adjustment (e.g., adds another ΔT into clock generator) (1008) and determines whether a sweep of the phase has completed (e.g., clock generator 702 has received P phase adjustments). If the phase sweep has not completed (e.g., clock generator 702 has received fewer than P phase adjustments) (1010), then jitter self-test circuit 704 continues to capture timestamps in memory 724 and digital processing circuit 708 continues to sort timestamps into the first set of timestamps and the second set of timestamps based on edges of clock-signal-under-test CLK_TEST and reference clock signal CLK_REF_TDC (1006). If the phase sweep has completed (e.g., i==P or ΔT==max ΔT) (1010), then digital processing circuit 708 calculates the standard deviation of the distribution of timestamps in the first set of timestamps or the second set of timestamps (1012). Since the jitter is proportional to the standard deviation, digital processing circuit 708 provides the standard deviation or a value based on the standard deviation and as an indicator of jitter of the clock-signal-under test. Digital processing circuit 708 outputs the jitter estimate, the standard deviation estimate, or an indication of whether the jitter satisfies a predetermined specification external to the integrated circuit product (1014). Note that the information and control flow of
Structures described herein may be implemented using software executing on a processor (which includes firmware) or by a combination of software and hardware. Software, as described herein, may be encoded in at least one tangible (i.e., non-transitory) computer readable medium. As referred to herein, a tangible computer-readable medium includes at least a disk, tape, or other magnetic, optical, or electronic storage medium. The tangible computer-readable media may store instructions as well as data that can be used to implement the invention. The instructions/data may be related to hardware, software, firmware or combinations thereof.
Thus, techniques for estimating jitter of a clock signal using a time-to-digital converter of an integrated circuit product are disclosed. The jitter self-test techniques are cheaper and faster than using a phase noise analyzer external to the integrated circuit product. The description of the invention set forth herein is illustrative and is not intended to limit the scope of the invention as set forth in the following claims. Variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein, without departing from the scope of the invention as set forth in the following claims.
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Number | Date | Country | |
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20210176020 A1 | Jun 2021 | US |