Keng L. Wong

Person

Hillsboro, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Split-biased interpolated voltage-controlled oscillator and phase l...
- Patent number 7,498,892
- Issue date Mar 3, 2009
- Intel Corporation
- Keng L. Wong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multi mode clock generator
- Patent number 7,408,420
- Issue date Aug 5, 2008
- Intel Corporation
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase-locked loop having dynamically adjustable up/down pulse widths
- Patent number 7,404,099
- Issue date Jul 22, 2008
- Intel Corporation
- Mingwei Huang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Controlling sequence of clock distribution to clock distribution do...
- Patent number 7,386,749
- Issue date Jun 10, 2008
- Intel Corporation
- Michael C. Rifani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-biased phased-locked loop
- Patent number 7,310,020
- Issue date Dec 18, 2007
- Intel Corporation
- Swee Boon Tan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Phase jitter measurement circuit
- Patent number 7,308,372
- Issue date Dec 11, 2007
- Intel Corporation
- Michael C. Rifani
- G01 - MEASURING TESTING
Information Patent Grant
Voltage control for clock generating circuit
- Patent number 7,242,261
- Issue date Jul 10, 2007
- Intel Corporation
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to dynamically change an operating frequency a...
- Patent number 7,237,128
- Issue date Jun 26, 2007
- Intel Corporation
- Alon Naveh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase locked loop system capable of deskewing
- Patent number 7,199,624
- Issue date Apr 3, 2007
- Intel Corporation
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Global I/O timing adjustment using calibrated delay elements
- Patent number 7,197,659
- Issue date Mar 27, 2007
- Intel Corporation
- Chee How Lim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-loop circuit capable of providing a delayed clock in phase lo...
- Patent number 7,184,503
- Issue date Feb 27, 2007
- Intel Corporation
- Keng L. Wong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Self-biased phased-locked loop
- Patent number 7,173,461
- Issue date Feb 6, 2007
- Intel Corporation
- Swee Boon Tan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Frequency-based slope-adjustment circuit
- Patent number 7,154,320
- Issue date Dec 26, 2006
- Intel Corporation
- Usman A. Mughal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Delay element calibration
- Patent number 7,024,324
- Issue date Apr 4, 2006
- Intel Corporation
- Michael C. Rifani
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for jitter reduction in phase locked loops
- Patent number 7,023,945
- Issue date Apr 4, 2006
- Intel Corporation
- Keng L. Wong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus to dynamically change an operating frequency a...
- Patent number 7,013,406
- Issue date Mar 14, 2006
- Intel Corporation
- Alon Naveh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock generating circuit and method
- Patent number 6,985,041
- Issue date Jan 10, 2006
- Intel Corporation
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for reducing lock time in dual charge-pump pha...
- Patent number 6,937,075
- Issue date Aug 30, 2005
- Intel Corporation
- Chee How Lim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for optimizing clock distribution to reduce th...
- Patent number 6,934,872
- Issue date Aug 23, 2005
- Intel Corporation
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Voltage ID based frequency control for clock generating circuit
- Patent number 6,924,710
- Issue date Aug 2, 2005
- Intel Corporation
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for fast lock acquisition in self-biased phase...
- Patent number 6,919,769
- Issue date Jul 19, 2005
- Intel Corporation
- Chee How Lim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Altering operating frequency and voltage set point of a circuit in...
- Patent number 6,885,233
- Issue date Apr 26, 2005
- Intel Corporation
- Douglas Robert Huard
- G05 - CONTROLLING REGULATING
Information Patent Grant
Multi-stage programmable Johnson counter
- Patent number 6,876,717
- Issue date Apr 5, 2005
- Intel Corporation
- Feng Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Cascaded phase-locked loops
- Patent number 6,842,056
- Issue date Jan 11, 2005
- Intel Corporation
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Voltage ID based frequency control for clock generating circuit
- Patent number 6,809,606
- Issue date Oct 26, 2004
- Intel Corporation
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Voltage control for clock generating circuit
- Patent number 6,778,033
- Issue date Aug 17, 2004
- Intel Corporation
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Frequency control for clock generating circuit
- Patent number 6,771,134
- Issue date Aug 3, 2004
- Intel Corporation
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clocking an I/O buffer, having a selectable phase difference from t...
- Patent number 6,748,549
- Issue date Jun 8, 2004
- Intel Corporation
- Chi-Yeu Chao
- G01 - MEASURING TESTING
Information Patent Grant
Variable lock window for a phase locked loop
- Patent number 6,614,317
- Issue date Sep 2, 2003
- Intel Corporation
- Keng L. Wong
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Reference timer for frequency measurement in a microprocessor
- Patent number 6,587,800
- Issue date Jul 1, 2003
- Intel Corporation
- Douglas R. Parker
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
Split-blased interpolated voltage-controlled oscillator and phase l...
- Publication number 20080231382
- Publication date Sep 25, 2008
- Keng L. Wong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Phase locked loop circuit
- Publication number 20070159223
- Publication date Jul 12, 2007
- Feng Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Self-biased phased-locked loop
- Publication number 20070152760
- Publication date Jul 5, 2007
- Intel Corporation
- Swee Boon Tan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Multi mode clock generator
- Publication number 20070069825
- Publication date Mar 29, 2007
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Self-biased phased-locked loop
- Publication number 20060267646
- Publication date Nov 30, 2006
- Intel Corporation
- Swee Boon Tan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Frequency-based slope-adjustment circuit
- Publication number 20060220713
- Publication date Oct 5, 2006
- Intel Corporation
- Usman A. Mughal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Controlling sequence of clock distribution to clock distribution do...
- Publication number 20060200694
- Publication date Sep 7, 2006
- Michael C. Rifani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus to dynamically change an operating frequency a...
- Publication number 20060156040
- Publication date Jul 13, 2006
- Alon Naveh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Phase jitter measurement circuit
- Publication number 20060122806
- Publication date Jun 8, 2006
- Michael C. Rifani
- G01 - MEASURING TESTING
Information Patent Application
Method and apparatus for jitter reduction in phase locked loops
- Publication number 20060091964
- Publication date May 4, 2006
- Keng L. Wong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Phase-locked loop having dynamically adjustable up/down pulse widths
- Publication number 20060034403
- Publication date Feb 16, 2006
- Mingwei Huang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Delay element calibration
- Publication number 20050278131
- Publication date Dec 15, 2005
- Michael C. Rifani
- G01 - MEASURING TESTING
Information Patent Application
Method and apparatus for fast lock acquisition in self-biased phase...
- Publication number 20050062548
- Publication date Mar 24, 2005
- Chee How Lim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CASCADED PHASE-LOCKED LOOPS
- Publication number 20040263223
- Publication date Dec 30, 2004
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for reducing lock time in dual charge-pump pha...
- Publication number 20040239386
- Publication date Dec 2, 2004
- Chee How Lim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Phase locked loop system capable of deskewing
- Publication number 20040217787
- Publication date Nov 4, 2004
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Voltage ID based frequency control for clock generating circuit
- Publication number 20040080347
- Publication date Apr 29, 2004
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Voltage control for clock generating circuit
- Publication number 20040070464
- Publication date Apr 15, 2004
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for jitter reduction in phase locked loops
- Publication number 20030231730
- Publication date Dec 18, 2003
- Keng L. Wong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Voltage ID based frequency control for clock generating circuit
- Publication number 20030206071
- Publication date Nov 6, 2003
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ALTERING OPERATING FREQUENCY AND VOLTAGE SET POINT OF A CIRCUIT IN...
- Publication number 20030206050
- Publication date Nov 6, 2003
- Douglas Robert Huard
- G05 - CONTROLLING REGULATING
Information Patent Application
Frequency control for clock generating circuit
- Publication number 20030206068
- Publication date Nov 6, 2003
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Voltage control for clock generating circuit
- Publication number 20030206072
- Publication date Nov 6, 2003
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock generating circuit and method
- Publication number 20030206067
- Publication date Nov 6, 2003
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for optimizing clock distribution to reduce th...
- Publication number 20030115493
- Publication date Jun 19, 2003
- Keng L. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Global I/O timing adjustment using calibrated delay elements
- Publication number 20030065962
- Publication date Apr 3, 2003
- Chee How Lim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Variable lock window for a phase locked loop
- Publication number 20020175769
- Publication date Nov 28, 2002
- Keng L. Wong
- H03 - BASIC ELECTRONIC CIRCUITRY

Keng L. Wong

Person

Patents Grantslast 30 patents

Split-biased interpolated voltage-controlled oscillator and phase l...

Multi mode clock generator

Phase-locked loop having dynamically adjustable up/down pulse widths

Controlling sequence of clock distribution to clock distribution do...

Self-biased phased-locked loop

Phase jitter measurement circuit

Voltage control for clock generating circuit

Method and apparatus to dynamically change an operating frequency a...

Phase locked loop system capable of deskewing

Global I/O timing adjustment using calibrated delay elements

Multi-loop circuit capable of providing a delayed clock in phase lo...

Self-biased phased-locked loop

Frequency-based slope-adjustment circuit

Delay element calibration

Method and apparatus for jitter reduction in phase locked loops

Method and apparatus to dynamically change an operating frequency a...

Clock generating circuit and method

Method and apparatus for reducing lock time in dual charge-pump pha...

Method and apparatus for optimizing clock distribution to reduce th...

Voltage ID based frequency control for clock generating circuit

Method and apparatus for fast lock acquisition in self-biased phase...

Altering operating frequency and voltage set point of a circuit in...

Multi-stage programmable Johnson counter

Cascaded phase-locked loops

Voltage ID based frequency control for clock generating circuit

Voltage control for clock generating circuit

Frequency control for clock generating circuit

Clocking an I/O buffer, having a selectable phase difference from t...

Variable lock window for a phase locked loop

Reference timer for frequency measurement in a microprocessor

Patents Applicationslast 30 patents

Split-blased interpolated voltage-controlled oscillator and phase l...

Phase locked loop circuit

Self-biased phased-locked loop

Multi mode clock generator

Self-biased phased-locked loop

Frequency-based slope-adjustment circuit

Controlling sequence of clock distribution to clock distribution do...

Method and apparatus to dynamically change an operating frequency a...

Phase jitter measurement circuit

Method and apparatus for jitter reduction in phase locked loops

Phase-locked loop having dynamically adjustable up/down pulse widths

Delay element calibration

Method and apparatus for fast lock acquisition in self-biased phase...

CASCADED PHASE-LOCKED LOOPS

Method and apparatus for reducing lock time in dual charge-pump pha...

Phase locked loop system capable of deskewing

Voltage ID based frequency control for clock generating circuit

Voltage control for clock generating circuit

Method and apparatus for jitter reduction in phase locked loops

Voltage ID based frequency control for clock generating circuit

ALTERING OPERATING FREQUENCY AND VOLTAGE SET POINT OF A CIRCUIT IN...

Frequency control for clock generating circuit

Voltage control for clock generating circuit

Clock generating circuit and method

Method and apparatus for optimizing clock distribution to reduce th...

Global I/O timing adjustment using calibrated delay elements

Variable lock window for a phase locked loop