Kent D. Hewitt

Person

Chandler, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Shared source line memory architecture for flash cell byte-alterabl...
- Patent number 10,910,058
- Issue date Feb 2, 2021
- Microchip Technology Incorporated
- Jen-I Pi
- G11 - INFORMATION STORAGE
Information Patent Grant
EEPROM memory cell with low voltage read path and high voltage eras...
- Patent number 9,455,037
- Issue date Sep 27, 2016
- Microchip Technology Incorporated
- Kent Hewitt
- G11 - INFORMATION STORAGE
Information Patent Grant
Resistive random access memory (ReRAM) and conductive bridging rand...
- Patent number 9,343,147
- Issue date May 17, 2016
- Microship Technology Incorporated
- Traian Bontas
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of programming an array of NMOS EEPROM cells that minimizes...
- Patent number 8,094,503
- Issue date Jan 10, 2012
- Microchip Technology Incorporated
- Jeffrey A. Shields
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for programming and erasing an array of NMOS EEPROM cells th...
- Patent number 7,817,474
- Issue date Oct 19, 2010
- Microchip Technology Incorporated
- Jeffrey A. Shields
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for programming and erasing an array of NMOS EEPROM cells th...
- Patent number 7,466,591
- Issue date Dec 16, 2008
- Microchip Technology Incorporated
- Jeffrey A. Shields
- G11 - INFORMATION STORAGE
Information Patent Grant
Independently programmable memory segments within a PMOS electrical...
- Patent number 6,504,191
- Issue date Jan 7, 2003
- Microchip Technology Incorporated
- Donald S. Gerber
- G11 - INFORMATION STORAGE
Information Patent Grant
Independently programmable memory segments within a PMOS electrical...
- Patent number 6,300,183
- Issue date Oct 9, 2001
- Microchip Technology Incorporated
- Donald S. Gerber
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming method for a memory cell
- Patent number 6,236,595
- Issue date May 22, 2001
- Microchip Technology Incorporated
- Donald S. Gerber
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for minimizing program disturb in a memory cell
- Patent number 6,222,761
- Issue date Apr 24, 2001
- Microchip Technology Incorporated
- Donald S. Gerber
- G11 - INFORMATION STORAGE
Information Patent Grant
Time delay circuit which is voltage independent
- Patent number 6,150,864
- Issue date Nov 21, 2000
- Randy L. Yach
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated voltage regulating circuit useful in high voltage electr...
- Patent number 5,764,099
- Issue date Jun 9, 1998
- Microchip Technology, Inc.
- Kent Hewitt
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Method and apparatus for electronic encoding and decoding
- Patent number 5,675,622
- Issue date Oct 7, 1997
- Microchip Technology Incorporated
- Kent Hewitt
- G07 - CHECKING-DEVICES
Information Patent Grant
Method and apparatus for preventing unauthorized access to nonvolat...
- Patent number 5,675,534
- Issue date Oct 7, 1997
- Microchip Technology Incorporated
- Kent Hewitt
- G11 - INFORMATION STORAGE
Information Patent Grant
Initializing a read pipeline of a non-volatile sequential memory de...
- Patent number 5,604,701
- Issue date Feb 18, 1997
- Microchip Technology Incorporated
- Samuel E. Alexander
- G11 - INFORMATION STORAGE
Information Patent Grant
Serial EEPROM device and associated method for reducing data load t...
- Patent number 5,488,711
- Issue date Jan 30, 1996
- Microchip Technology Incorporated
- Kent D. Hewitt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable high endurance block for EEPROM device
- Patent number 5,367,484
- Issue date Nov 22, 1994
- Microchip Technology Incorporated
- Samuel E. Alexander
- G11 - INFORMATION STORAGE
Information Patent Grant
Write protection security for memory device
- Patent number 5,363,334
- Issue date Nov 8, 1994
- Microchip Technology Incorporated
- Samuel E. Alexander
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SHARED SOURCE LINE MEMORY ARCHITECTURE FOR FLASH CELL BYTE-ALTERABL...
- Publication number 20200058355
- Publication date Feb 20, 2020
- MICROCHIP TECHNOLOGY INCORPORATED
- Jen-I Pi
- G11 - INFORMATION STORAGE
Information Patent Application
EEPROM MEMORY CELL WITH LOW VOLTAGE READ PATH AND HIGH VOLTAGE ERAS...
- Publication number 20140269102
- Publication date Sep 18, 2014
- MICROCHIP TECHNOLOGY INCORPORATED
- Kent Hewitt
- G11 - INFORMATION STORAGE
Information Patent Application
Resistive Random Access Memory (RERAM) and Conductive Bridging Rand...
- Publication number 20140254244
- Publication date Sep 11, 2014
- Traian Bontas
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF PROGRAMMING AN ARRAY OF NMOS EEPROM CELLS THAT MINIMIZES...
- Publication number 20100302857
- Publication date Dec 2, 2010
- MICROCHIP TECHNOLOGY INCORPORATED
- Jeffrey A. Shields
- G11 - INFORMATION STORAGE
Information Patent Application
Method for Programming and Erasing an Array of NMOS EEPROM Cells th...
- Publication number 20090122618
- Publication date May 14, 2009
- MICROCHIP TECHNOLOGY INCORPORATED
- Jeffrey A. Shields
- G11 - INFORMATION STORAGE
Information Patent Application
Method for Programming and Erasing an Array of NMOS EEPROM Cells Th...
- Publication number 20070280001
- Publication date Dec 6, 2007
- MICROCHIP TECHNOLOGY INCORPORATED
- Jeffrey A. Shields
- G11 - INFORMATION STORAGE
Information Patent Application
Independently programmable memory segments within an NMOS electrica...
- Publication number 20070140008
- Publication date Jun 21, 2007
- MICROCHIP TECHNOLOGY INCORPORATED
- Jeffrey Shields
- G11 - INFORMATION STORAGE
Information Patent Application
Independently programmable memory segments within a PMOS electrical...
- Publication number 20020014642
- Publication date Feb 7, 2002
- Donald S. Gerber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for minimizing program disturb in a memory cell
- Publication number 20020006059
- Publication date Jan 17, 2002
- Donald S. Gerber
- G11 - INFORMATION STORAGE

Kent D. Hewitt

Person

Patents Grantslast 30 patents

Shared source line memory architecture for flash cell byte-alterabl...

EEPROM memory cell with low voltage read path and high voltage eras...

Resistive random access memory (ReRAM) and conductive bridging rand...

Method of programming an array of NMOS EEPROM cells that minimizes...

Method for programming and erasing an array of NMOS EEPROM cells th...

Method for programming and erasing an array of NMOS EEPROM cells th...

Independently programmable memory segments within a PMOS electrical...

Independently programmable memory segments within a PMOS electrical...

Programming method for a memory cell

Method for minimizing program disturb in a memory cell

Time delay circuit which is voltage independent

Integrated voltage regulating circuit useful in high voltage electr...

Method and apparatus for electronic encoding and decoding

Method and apparatus for preventing unauthorized access to nonvolat...

Initializing a read pipeline of a non-volatile sequential memory de...

Serial EEPROM device and associated method for reducing data load t...

Programmable high endurance block for EEPROM device

Write protection security for memory device

Patents Applicationslast 30 patents

SHARED SOURCE LINE MEMORY ARCHITECTURE FOR FLASH CELL BYTE-ALTERABL...

EEPROM MEMORY CELL WITH LOW VOLTAGE READ PATH AND HIGH VOLTAGE ERAS...

Resistive Random Access Memory (RERAM) and Conductive Bridging Rand...

METHOD OF PROGRAMMING AN ARRAY OF NMOS EEPROM CELLS THAT MINIMIZES...

Method for Programming and Erasing an Array of NMOS EEPROM Cells th...

Method for Programming and Erasing an Array of NMOS EEPROM Cells Th...

Independently programmable memory segments within an NMOS electrica...

Independently programmable memory segments within a PMOS electrical...

Method for minimizing program disturb in a memory cell