Kerry Dean Tedrow

Person

Folsom, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory tile access and selection patterns
- Patent number 10,942,873
- Issue date Mar 9, 2021
- Micron Technology, Inc.
- Hernan A. Castro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory sense amplifiers and memory verification methods
- Patent number 10,748,613
- Issue date Aug 18, 2020
- Micron Technology, Inc.
- Makoto Kitagawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory tile access and selection patterns
- Patent number 10,387,338
- Issue date Aug 20, 2019
- Micron Technology, Inc.
- Hernan A. Castro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory sense amplifiers and memory verification methods
- Patent number 10,147,487
- Issue date Dec 4, 2018
- Micron Technology, Inc.
- Makoto Kitagawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory tile access and selection patterns
- Patent number 9,959,220
- Issue date May 1, 2018
- Micron Technology, Inc.
- Hernan A. Castro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory cell verification circuits, memory cell sense circuits and m...
- Patent number 9,799,398
- Issue date Oct 24, 2017
- Micron Technology, Inc.
- Makoto Kitagawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory tile access and selection patterns
- Patent number 9,626,292
- Issue date Apr 18, 2017
- Micron Technology, Inc.
- Hernan A. Castro
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device comprising double cascode sense amplifiers
- Patent number 9,564,181
- Issue date Feb 7, 2017
- SONY SEMICONDUCTOR SOLUTIONS CORPORATION
- Kerry Tedrow
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual mode clock and data scheme for memory programming
- Patent number 9,437,288
- Issue date Sep 6, 2016
- Micron Technology, Inc.
- Kerry Dean Tedrow
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory tile access and selection patterns
- Patent number 9,406,362
- Issue date Aug 2, 2016
- Micron Technology, Inc.
- Hernan A. Castro
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory sense amplifiers and memory verification methods
- Patent number 9,311,999
- Issue date Apr 12, 2016
- Micron Technology, Inc.
- Makoto Kitagawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual mode clock and data scheme for memory programming
- Patent number 8,804,411
- Issue date Aug 12, 2014
- Micron Technology, Inc.
- Kerry Dean Tedrow
- G11 - INFORMATION STORAGE
Information Patent Grant
Phase-change memory temperature sensitive detector
- Patent number 8,259,488
- Issue date Sep 4, 2012
- Micron Technology, Inc.
- Kerry Dean Tedrow
- G11 - INFORMATION STORAGE
Information Patent Grant
Dedicated interface to factory program phase-change memories
- Patent number 8,176,232
- Issue date May 8, 2012
- Micron Technology, Inc.
- Kerry Dean Tedrow
- G11 - INFORMATION STORAGE
Information Patent Grant
Switched bitline VTH sensing for non-volatile memories
- Patent number 8,059,468
- Issue date Nov 15, 2011
- Intel Corporation
- Nicholas T. Hendrickson
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-level memory cell sensing
- Patent number 7,551,489
- Issue date Jun 23, 2009
- Intel Corporation
- Kerry D. Tedrow
- G11 - INFORMATION STORAGE
Information Patent Grant
Control circuit for refreshing voltages in a non-volatile memory du...
- Patent number 7,525,865
- Issue date Apr 28, 2009
- Intel Corporation
- Bharat Chauhan
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array with pseudo single bit memory cell and method
- Patent number 7,525,840
- Issue date Apr 28, 2009
- Intel Corporation
- Ahsanur Rahman
- G11 - INFORMATION STORAGE
Information Patent Grant
Negatively biasing deselected memory cells
- Patent number 7,319,616
- Issue date Jan 15, 2008
- Intel Corporation
- Rajesh Sundaram
- G11 - INFORMATION STORAGE
Information Patent Grant
Step voltage generation
- Patent number 7,313,019
- Issue date Dec 25, 2007
- Intel Corporation
- Hari Giduturi
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array with pseudo single bit memory cell and method
- Patent number 7,272,041
- Issue date Sep 18, 2007
- Intel Corporation
- Ahsanur Rahman
- G11 - INFORMATION STORAGE
Information Patent Grant
Voltage reference apparatus, method, and system
- Patent number 7,176,751
- Issue date Feb 13, 2007
- Intel Corporation
- Hari Giduturi
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and methods for pre-charging intermediate nodes for hig...
- Patent number 7,139,205
- Issue date Nov 21, 2006
- Intel Corporation
- Matthew Goldman
- G11 - INFORMATION STORAGE
Information Patent Grant
High precision reference devices and methods
- Patent number 7,116,597
- Issue date Oct 3, 2006
- Intel Corporation
- Matthew Goldman
- G11 - INFORMATION STORAGE
Information Patent Grant
Method, apparatus, and system to enhance negative voltage switching
- Patent number 6,944,065
- Issue date Sep 13, 2005
- Intel Corporation
- Kerry D. Tedrow
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for matched-reference sensing architecture for...
- Patent number 6,831,862
- Issue date Dec 14, 2004
- Intel Corporation
- Kerry D. Tedrow
- G11 - INFORMATION STORAGE
Information Patent Grant
Method, apparatus, and system to enhance negative voltage switching
- Patent number 6,788,584
- Issue date Sep 7, 2004
- Intel Corporation
- Kerry D. Tedrow
- G11 - INFORMATION STORAGE
Information Patent Grant
Block-level read while write method and apparatus
- Patent number 6,772,273
- Issue date Aug 3, 2004
- Intel Corporation
- Kerry D. Tedrow
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming non-volatile memory devices
- Patent number 6,700,820
- Issue date Mar 2, 2004
- Intel Corporation
- Daniel R. Elmhurst
- G11 - INFORMATION STORAGE
Information Patent Grant
Reference voltage generator employing large flash memory cells coup...
- Patent number 6,697,282
- Issue date Feb 24, 2004
- Intel Corporation
- Stephen N. Keeney
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY TILE ACCESS AND SELECTION PATTERNS
- Publication number 20200012606
- Publication date Jan 9, 2020
- Micron Technology, Inc.
- Hernan A. Castro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Sense Amplifiers and Memory Verification Methods
- Publication number 20190066783
- Publication date Feb 28, 2019
- Micron Technology, Inc.
- Makoto Kitagawa
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY TILE ACCESS AND SELECTION PATTERNS
- Publication number 20180285287
- Publication date Oct 4, 2018
- Micron Technology, Inc.
- Hernan A. Castro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Sense Amplifiers and Memory Verification Methods
- Publication number 20180047446
- Publication date Feb 15, 2018
- Micron Technology, Inc.
- Makoto Kitagawa
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY TILE ACCESS AND SELECTION PATTERNS
- Publication number 20170192911
- Publication date Jul 6, 2017
- Micron Technology, Inc.
- Hernan A. Castro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY TILE ACCESS AND SELECTION PATTERNS
- Publication number 20160306740
- Publication date Oct 20, 2016
- Micron Technology, Inc.
- Hernan A. Castro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Sense Amplifiers and Memory Verification Methods
- Publication number 20160225444
- Publication date Aug 4, 2016
- Micron Technology, Inc.
- Makoto Kitagawa
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Sense Amplifiers and Memory Verification Methods
- Publication number 20150070972
- Publication date Mar 12, 2015
- Micron Technology, Inc.
- Makoto Kitagawa
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE COMPRISING DOUBLE CASCODE SENSE AMPLIFIERS
- Publication number 20150071011
- Publication date Mar 12, 2015
- SONY CORPORATION
- Kerry Tedrow
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY TILE ACCESS AND SELECTION PATTERNS
- Publication number 20140372713
- Publication date Dec 18, 2014
- Hernan A. Castro
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL MODE CLOCK AND DATA SCHEME FOR MEMORY PROGRAMMING
- Publication number 20140347920
- Publication date Nov 27, 2014
- Kerry Dean Tedrow
- G11 - INFORMATION STORAGE
Information Patent Application
DEDICATED INTERFACE TO FACTORY PROGRAM PHASE-CHANGE MEMORIES
- Publication number 20100287435
- Publication date Nov 11, 2010
- Kerry Dean Tedrow
- G11 - INFORMATION STORAGE
Information Patent Application
CONTROL CIRCUIT FOR REFRESHING VOLTAGES IN A NON-VOLATILE MEMORY DU...
- Publication number 20090003116
- Publication date Jan 1, 2009
- Intel Corporation
- Bharat CHAUHAN
- G11 - INFORMATION STORAGE
Information Patent Application
Switched bitline VTH sensing for non-volatile memories
- Publication number 20080273397
- Publication date Nov 6, 2008
- Nicholas T. Hendrickson
- G11 - INFORMATION STORAGE
Information Patent Application
Reducing read disturb in non-volatile multiple- level cell memories
- Publication number 20080117675
- Publication date May 22, 2008
- Rezaul Haque
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Array with Psedudo Single Bit Memory Cell and Method
- Publication number 20070268758
- Publication date Nov 22, 2007
- Intel Corporation
- Ahsanur Rahman
- G11 - INFORMATION STORAGE
Information Patent Application
Multi-level memory cell sensing
- Publication number 20070171708
- Publication date Jul 26, 2007
- Kerry D. Tedrow
- G11 - INFORMATION STORAGE
Information Patent Application
Memory array with pseudo single bit memory cell and method
- Publication number 20070002613
- Publication date Jan 4, 2007
- Intel Corporation
- Ahsanur Rahman
- G11 - INFORMATION STORAGE
Information Patent Application
Analog counter using memory cell
- Publication number 20060156097
- Publication date Jul 13, 2006
- Christian A. Camarce
- G11 - INFORMATION STORAGE
Information Patent Application
Step voltage generation
- Publication number 20060132114
- Publication date Jun 22, 2006
- Hari Giduturi
- G11 - INFORMATION STORAGE
Information Patent Application
Voltage reference apparatus, method, and system
- Publication number 20060114054
- Publication date Jun 1, 2006
- Hari Giduturi
- G05 - CONTROLLING REGULATING
Information Patent Application
Data latch pre-equalization
- Publication number 20050285631
- Publication date Dec 29, 2005
- Intel Corporation
- Matthew Goldman
- G11 - INFORMATION STORAGE
Information Patent Application
Negatively biasing deselected memory cells
- Publication number 20050105338
- Publication date May 19, 2005
- Rajesh Sundaram
- G11 - INFORMATION STORAGE
Information Patent Application
Method, apparatus, and system to enhance negative voltage switching
- Publication number 20040228192
- Publication date Nov 18, 2004
- Kerry D. Tedrow
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus to provide a low voltage reference generation
- Publication number 20030208699
- Publication date Nov 6, 2003
- Mase Taub
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programming non-volatile memory devices
- Publication number 20030123295
- Publication date Jul 3, 2003
- Daniel R. Elmhurst
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for matched-reference sensing architecture for...
- Publication number 20030090949
- Publication date May 15, 2003
- Kerry D. Tedrow
- G11 - INFORMATION STORAGE
Information Patent Application
CHARGING A CAPACITANCE OF A MEMORY CELL AND CHARGER
- Publication number 20030002341
- Publication date Jan 2, 2003
- Kerry D. Tedrow
- G11 - INFORMATION STORAGE
Information Patent Application
Charging a capacitance of a memory cell and charger
- Publication number 20030002374
- Publication date Jan 2, 2003
- Kerry D. Tedrow
- G11 - INFORMATION STORAGE
Information Patent Application
Method, apparatus, and system to enhance negative voltage switching
- Publication number 20020141250
- Publication date Oct 3, 2002
- Kerry D. Tedrow
- G11 - INFORMATION STORAGE

Kerry Dean Tedrow

Person

Patents Grantslast 30 patents

Memory tile access and selection patterns

Memory sense amplifiers and memory verification methods

Memory tile access and selection patterns

Memory sense amplifiers and memory verification methods

Memory tile access and selection patterns

Memory cell verification circuits, memory cell sense circuits and m...

Memory tile access and selection patterns

Memory device comprising double cascode sense amplifiers

Dual mode clock and data scheme for memory programming

Memory tile access and selection patterns

Memory sense amplifiers and memory verification methods

Dual mode clock and data scheme for memory programming

Phase-change memory temperature sensitive detector

Dedicated interface to factory program phase-change memories

Switched bitline VTH sensing for non-volatile memories

Multi-level memory cell sensing

Control circuit for refreshing voltages in a non-volatile memory du...

Memory array with pseudo single bit memory cell and method

Negatively biasing deselected memory cells

Step voltage generation

Memory array with pseudo single bit memory cell and method

Voltage reference apparatus, method, and system

Apparatuses and methods for pre-charging intermediate nodes for hig...

High precision reference devices and methods

Method, apparatus, and system to enhance negative voltage switching

Method and apparatus for matched-reference sensing architecture for...

Method, apparatus, and system to enhance negative voltage switching

Block-level read while write method and apparatus

Programming non-volatile memory devices

Reference voltage generator employing large flash memory cells coup...

Patents Applicationslast 30 patents

MEMORY TILE ACCESS AND SELECTION PATTERNS

Memory Sense Amplifiers and Memory Verification Methods

MEMORY TILE ACCESS AND SELECTION PATTERNS

Memory Sense Amplifiers and Memory Verification Methods

MEMORY TILE ACCESS AND SELECTION PATTERNS

MEMORY TILE ACCESS AND SELECTION PATTERNS

Memory Sense Amplifiers and Memory Verification Methods

Memory Sense Amplifiers and Memory Verification Methods

MEMORY DEVICE COMPRISING DOUBLE CASCODE SENSE AMPLIFIERS

MEMORY TILE ACCESS AND SELECTION PATTERNS

DUAL MODE CLOCK AND DATA SCHEME FOR MEMORY PROGRAMMING

DEDICATED INTERFACE TO FACTORY PROGRAM PHASE-CHANGE MEMORIES

CONTROL CIRCUIT FOR REFRESHING VOLTAGES IN A NON-VOLATILE MEMORY DU...

Switched bitline VTH sensing for non-volatile memories

Reducing read disturb in non-volatile multiple- level cell memories

Memory Array with Psedudo Single Bit Memory Cell and Method

Multi-level memory cell sensing

Memory array with pseudo single bit memory cell and method

Analog counter using memory cell

Step voltage generation

Voltage reference apparatus, method, and system

Data latch pre-equalization

Negatively biasing deselected memory cells

Method, apparatus, and system to enhance negative voltage switching

Method and apparatus to provide a low voltage reference generation

Programming non-volatile memory devices

Method and apparatus for matched-reference sensing architecture for...

CHARGING A CAPACITANCE OF A MEMORY CELL AND CHARGER

Charging a capacitance of a memory cell and charger

Method, apparatus, and system to enhance negative voltage switching