Kevin T. Look

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Localization of failure in high density test structure
- Patent number 9,041,409
- Issue date May 26, 2015
- Xilinx, Inc.
- Kevin T. Look
- G01 - MEASURING TESTING
Information Patent Grant
Regulating unused/inactive resources in programmable logic devices...
- Patent number 7,504,854
- Issue date Mar 17, 2009
- Xilinx, Inc.
- Kevin T. Look
- G11 - INFORMATION STORAGE
Information Patent Grant
Single event upset in SRAM cells in FPGAs with high resistivity gat...
- Patent number 7,452,765
- Issue date Nov 18, 2008
- Xilinx, Inc.
- Martin L. Voogel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low voltage non-volatile memory transistor
- Patent number 7,092,273
- Issue date Aug 15, 2006
- Xilinx Inc.
- Kevin T. Look
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low voltage non-volatile memory transistor
- Patent number 7,026,692
- Issue date Apr 11, 2006
- Xilinx, Inc.
- Kevin T. Look
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Single event upset in SRAM cells in FPGAs with high resistivity gat...
- Patent number 6,982,451
- Issue date Jan 3, 2006
- Xilinx, Inc.
- Martin L. Voogel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low voltage non-volatile memory cell
- Patent number 6,936,527
- Issue date Aug 30, 2005
- Xilinx, Inc.
- Kevin T. Look
- G11 - INFORMATION STORAGE
Information Patent Grant
Low voltage non-volatile memory cell
- Patent number 6,930,920
- Issue date Aug 16, 2005
- Xilinx, Inc.
- Kevin T. Look
- G11 - INFORMATION STORAGE
Information Patent Grant
Low voltage non-volatile memory cell
- Patent number 6,882,571
- Issue date Apr 19, 2005
- Xilinx, Inc.
- Kevin T. Look
- G11 - INFORMATION STORAGE
Information Patent Grant
Mask-alignment detection circuit in X and Y directions
- Patent number 6,878,561
- Issue date Apr 12, 2005
- Xilinx, Inc.
- Kevin T. Look
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Mask alignment structure for IC layers
- Patent number 6,716,653
- Issue date Apr 6, 2004
- Xilinx, Inc.
- Kevin T. Look
- G01 - MEASURING TESTING
Information Patent Grant
Mask-alignment detection circuit in x and y directions
- Patent number 6,684,520
- Issue date Feb 3, 2004
- Xilinx, Inc.
- Kevin T. Look
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low voltage non-volatile memory cell
- Patent number 6,671,205
- Issue date Dec 30, 2003
- Xilinx, Inc.
- Kevin T. Look
- G11 - INFORMATION STORAGE
Information Patent Grant
Reticle cover for preventing ESD damage
- Patent number 6,569,576
- Issue date May 27, 2003
- Xilinx, Inc.
- Shih-Cheng Hsueh
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Mask alignment structure for IC layers
- Patent number 6,563,320
- Issue date May 13, 2003
- Xilinx, Inc.
- Kevin T. Look
- G01 - MEASURING TESTING
Information Patent Grant
Non-volatile memory array using gate breakdown structures
- Patent number 6,549,458
- Issue date Apr 15, 2003
- Xilinx, Inc.
- Kameswara K. Rao
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory array using gate breakdown structures
- Patent number 6,522,582
- Issue date Feb 18, 2003
- Xilinx, Inc.
- Kameswara K. Rao
- G11 - INFORMATION STORAGE
Information Patent Grant
Low voltage non-volatile memory cell
- Patent number 6,496,416
- Issue date Dec 17, 2002
- Xilinx, Inc.
- Kevin T. Look
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and circuits employing threshold voltages for mask-alignmen...
- Patent number 6,465,305
- Issue date Oct 15, 2002
- Xilinx, Inc.
- Kevin T. Look
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and circuits for mask-alignment detection
- Patent number 6,436,726
- Issue date Aug 20, 2002
- Xilinx, Inc.
- Kevin T. Look
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Methods and circuits employing threshold voltages for mask-alignmen...
- Patent number 6,426,534
- Issue date Jul 30, 2002
- Xilinx, Inc.
- Kevin T. Look
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Resistor arrays for mask-alignment detection
- Patent number 6,393,714
- Issue date May 28, 2002
- Xilinx, Inc.
- Kevin T. Look
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Methods and circuits for mask-alignment detection
- Patent number 6,305,095
- Issue date Oct 23, 2001
- Xilinx, Inc.
- Kevin T. Look
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method for over-etching to improve voltage distribution
- Patent number 6,057,589
- Issue date May 2, 2000
- Xilinx, Inc.
- Kevin T. Look
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming multilayer amorphous silicon antifuse
- Patent number 5,970,372
- Issue date Oct 19, 1999
- Xilinx, Inc.
- Michael J. Hart
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for over-etching to improve voltage distribution
- Patent number 5,786,240
- Issue date Jul 28, 1998
- Xilinx, Inc.
- Kevin T. Look
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multilayer amorphous silicon antifuse
- Patent number 5,726,484
- Issue date Mar 10, 1998
- Xilinx, Inc.
- Michael J. Hart
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a antifuse structure with increased breakdown at...
- Patent number 5,502,000
- Issue date Mar 26, 1996
- Xilinx, Inc.
- Kevin T. Look
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Antifuse structure with double oxide layers
- Patent number 5,486,707
- Issue date Jan 23, 1996
- Xilinx, Inc.
- Kevin T. Look
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Antifuse structure with increased breakdown at edges
- Patent number 5,475,253
- Issue date Dec 12, 1995
- Xilinx, Inc.
- Kevin T. Look
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
LOW VOLTAGE NON-VOLATILE MEMORY TRANSISTOR
- Publication number 20060134839
- Publication date Jun 22, 2006
- Xilinx, Inc.
- Kevin T. Look
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Mask-alignment detection circuit in X and Y directions
- Publication number 20040072398
- Publication date Apr 15, 2004
- Xilinx, Inc.
- Kevin T. Look
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Mask alignment structure for IC layers
- Publication number 20030049872
- Publication date Mar 13, 2003
- Xilinx, Inc.
- Kevin T. Look
- G01 - MEASURING TESTING
Information Patent Application
Low voltage non-volatile memory cell
- Publication number 20030048663
- Publication date Mar 13, 2003
- Xilinx, Inc.
- Kevin T. Look
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods and circuits for mask-alignment detection
- Publication number 20010049881
- Publication date Dec 13, 2001
- Xilinx, Inc.
- Kevin T. Look
- G01 - MEASURING TESTING

Kevin T. Look

Person

Patents Grantslast 30 patents

Localization of failure in high density test structure

Regulating unused/inactive resources in programmable logic devices...

Single event upset in SRAM cells in FPGAs with high resistivity gat...

Low voltage non-volatile memory transistor

Low voltage non-volatile memory transistor

Single event upset in SRAM cells in FPGAs with high resistivity gat...

Low voltage non-volatile memory cell

Low voltage non-volatile memory cell

Low voltage non-volatile memory cell

Mask-alignment detection circuit in X and Y directions

Mask alignment structure for IC layers

Mask-alignment detection circuit in x and y directions

Low voltage non-volatile memory cell

Reticle cover for preventing ESD damage

Mask alignment structure for IC layers

Non-volatile memory array using gate breakdown structures

Non-volatile memory array using gate breakdown structures

Low voltage non-volatile memory cell

Methods and circuits employing threshold voltages for mask-alignmen...

Methods and circuits for mask-alignment detection

Methods and circuits employing threshold voltages for mask-alignmen...

Resistor arrays for mask-alignment detection

Methods and circuits for mask-alignment detection

Method for over-etching to improve voltage distribution

Method of forming multilayer amorphous silicon antifuse

Method for over-etching to improve voltage distribution

Multilayer amorphous silicon antifuse

Method of forming a antifuse structure with increased breakdown at...

Antifuse structure with double oxide layers

Antifuse structure with increased breakdown at edges

Patents Applicationslast 30 patents

LOW VOLTAGE NON-VOLATILE MEMORY TRANSISTOR

Mask-alignment detection circuit in X and Y directions

Mask alignment structure for IC layers

Low voltage non-volatile memory cell

Methods and circuits for mask-alignment detection