Khaled El-Ayat

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Programmable system on a chip
- Patent number 7,937,601
- Issue date May 3, 2011
- Actel Corporation
- Greg Bakker
- G01 - MEASURING TESTING
Information Patent Grant
Programmable system on a chip
- Patent number 7,613,943
- Issue date Nov 3, 2009
- Actel Corporation
- Greg Bakker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable system on a chip
- Patent number 7,487,376
- Issue date Feb 3, 2009
- Actel Corporation
- Greg Bakker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable system on a chip
- Patent number 7,170,315
- Issue date Jan 30, 2007
- Actel Corporation
- Greg Bakker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable multi-standard I/O architecture for FPGAS
- Patent number 6,909,306
- Issue date Jun 21, 2005
- Actel Corporation
- Khaled A. El-Ayat
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable multi-standard I/O architecture for FPGAs
- Patent number 6,762,621
- Issue date Jul 13, 2004
- Actel Corporation
- Khaled A. El-Ayat
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable multi-standard I/O architecture for FPGAs
- Patent number 6,617,875
- Issue date Sep 9, 2003
- Actel Corporation
- Khaled A. El-Ayat
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable multi-standard I/O architecture for FPGAs
- Patent number 6,392,437
- Issue date May 21, 2002
- Actel Corporation
- Khaled Ahmad El-Ayat
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable multi-standard I/O architecture for FPGAS
- Patent number 6,242,943
- Issue date Jun 5, 2001
- Khaled Ahmad El-Ayat
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuits for testing the function circuit modules in an integrated...
- Patent number 5,804,960
- Issue date Sep 8, 1998
- Actel Corporation
- Khaled El Ayat
- G01 - MEASURING TESTING
Information Patent Grant
Programmable logic module and architecture for field programmable g...
- Patent number 5,698,992
- Issue date Dec 16, 1997
- Actel Corporation
- Khaled A. El Ayat
- G01 - MEASURING TESTING
Information Patent Grant
Flexible FPGA input/output architecture
- Patent number 5,625,301
- Issue date Apr 29, 1997
- Actel Corporation
- William C. Plants
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Testability circuits for logic circuit arrays
- Patent number 5,614,818
- Issue date Mar 25, 1997
- Actel Corporation
- Khaled El Ayat
- G01 - MEASURING TESTING
Information Patent Grant
Programmable logic module and architecture for field programmable g...
- Patent number 5,606,267
- Issue date Feb 25, 1997
- Actel Corporation
- Khaled A. El Ayat
- G01 - MEASURING TESTING
Information Patent Grant
Programmable interconnect architecture
- Patent number 5,600,265
- Issue date Feb 4, 1997
- Actel Corporation
- Abbas El Gamal
- G01 - MEASURING TESTING
Information Patent Grant
Testability circuits for logic arrays
- Patent number 5,528,600
- Issue date Jun 18, 1996
- Actel Corporation
- Khaled El Ayat
- G01 - MEASURING TESTING
Information Patent Grant
User-configurable logic circuits comprising antifuses and multiplex...
- Patent number 5,479,113
- Issue date Dec 26, 1995
- Actel Corporation
- Abbas E. Gamal
- G01 - MEASURING TESTING
Information Patent Grant
Programmable logic module and architecture for field programmable g...
- Patent number 5,477,165
- Issue date Dec 19, 1995
- Actel Corporation
- Khaled A. ElAyat
- G01 - MEASURING TESTING
Information Patent Grant
Testability architecture and techniques for programmable interconne...
- Patent number 5,432,441
- Issue date Jul 11, 1995
- Actel Corporation
- Khaled A. El-Ayat
- G01 - MEASURING TESTING
Information Patent Grant
Clock distribution scheme for user-programmable logic array archite...
- Patent number 5,391,942
- Issue date Feb 21, 1995
- Actel Corporation
- Khaled A. El-Ayat
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Testability architecture and techniques for programmable interconne...
- Patent number 5,365,165
- Issue date Nov 15, 1994
- Actel Corporation
- Khaled A. El-Ayat
- G01 - MEASURING TESTING
Information Patent Grant
Testability architecture and techniques for programmable interconne...
- Patent number 5,341,092
- Issue date Aug 23, 1994
- Actel Corporation
- Khaled A. El-Ayat
- G01 - MEASURING TESTING
Information Patent Grant
Testability architecture and techniques for programmable interconne...
- Patent number 5,309,091
- Issue date May 3, 1994
- Actel Corporation
- Khaled A. El-Ayat
- G01 - MEASURING TESTING
Information Patent Grant
Programmable interconnect architecture employing leaky programmable...
- Patent number 5,304,871
- Issue date Apr 19, 1994
- Actel Corporation
- Kuthanur R. Dharmarajan
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock distribution scheme for user-programmable logic array archite...
- Patent number 5,254,886
- Issue date Oct 19, 1993
- Actel Corporation
- Khaled A. El-Ayat
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Testability architecture and techniques for programmable interconne...
- Patent number 5,223,792
- Issue date Jun 29, 1993
- Actel Corporation
- Khaled A. El-Ayat
- G01 - MEASURING TESTING
Information Patent Grant
Testability architecture and techniques for programmable interconne...
- Patent number 5,208,530
- Issue date May 4, 1993
- Actel Corporation
- Khaled A. El-Ayat
- G01 - MEASURING TESTING
Information Patent Grant
Methods for preventing disturbance of antifuses during programming
- Patent number 5,194,759
- Issue date Mar 16, 1993
- Actel Corporation
- Khaled A. El-Ayat
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable interconnect architecture
- Patent number 5,172,014
- Issue date Dec 15, 1992
- Actel Corporation
- Khaled El Ayat
- G01 - MEASURING TESTING
Information Patent Grant
Mixed mode analog/digital programmable interconnect architecture
- Patent number 5,107,146
- Issue date Apr 21, 1992
- Actel Corporation
- Khaled A. El-Ayat
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PROGRAMMABLE SYSTEM ON A CHIP
- Publication number 20090292937
- Publication date Nov 26, 2009
- Actel Corporation
- Greg Bakker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE SYSTEM ON A CHIP
- Publication number 20080122481
- Publication date May 29, 2008
- Actel Corporation
- Greg Bakker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE SYSTEM ON A CHIP
- Publication number 20080048717
- Publication date Feb 28, 2008
- Actel Corporation
- Greg Bakker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE SYSTEM ON A CHIP
- Publication number 20070176631
- Publication date Aug 2, 2007
- Actel Corporation
- Greg Bakker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Programmable multi-standard I/O architecture for FPGAs
- Publication number 20030160632
- Publication date Aug 28, 2003
- Actel Corporation
- Khaled A. El-Ayat
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable multi-standard I/O architecture for FPGAs
- Publication number 20030016051
- Publication date Jan 23, 2003
- Khaled A. El-Ayat
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Programmable multi-standard I/O architecture for FPGAs
- Publication number 20010002796
- Publication date Jun 7, 2001
- Khaled Ahmad El-Ayat
- H03 - BASIC ELECTRONIC CIRCUITRY

Khaled El-Ayat

Person

Patents Grantslast 30 patents

Programmable system on a chip

Programmable system on a chip

Programmable system on a chip

Programmable system on a chip

Programmable multi-standard I/O architecture for FPGAS

Programmable multi-standard I/O architecture for FPGAs

Programmable multi-standard I/O architecture for FPGAs

Programmable multi-standard I/O architecture for FPGAs

Programmable multi-standard I/O architecture for FPGAS

Circuits for testing the function circuit modules in an integrated...

Programmable logic module and architecture for field programmable g...

Flexible FPGA input/output architecture

Testability circuits for logic circuit arrays

Programmable logic module and architecture for field programmable g...

Programmable interconnect architecture

Testability circuits for logic arrays

User-configurable logic circuits comprising antifuses and multiplex...

Programmable logic module and architecture for field programmable g...

Testability architecture and techniques for programmable interconne...

Clock distribution scheme for user-programmable logic array archite...

Testability architecture and techniques for programmable interconne...

Testability architecture and techniques for programmable interconne...

Testability architecture and techniques for programmable interconne...

Programmable interconnect architecture employing leaky programmable...

Clock distribution scheme for user-programmable logic array archite...

Testability architecture and techniques for programmable interconne...

Testability architecture and techniques for programmable interconne...

Methods for preventing disturbance of antifuses during programming

Programmable interconnect architecture

Mixed mode analog/digital programmable interconnect architecture

Patents Applicationslast 30 patents

PROGRAMMABLE SYSTEM ON A CHIP

PROGRAMMABLE SYSTEM ON A CHIP

PROGRAMMABLE SYSTEM ON A CHIP

PROGRAMMABLE SYSTEM ON A CHIP

Programmable multi-standard I/O architecture for FPGAs

Programmable multi-standard I/O architecture for FPGAs

Programmable multi-standard I/O architecture for FPGAs