Kim C. Hardee

Person

Colorado Springs, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
Calibration circuit for on-chip drive and on-die termination
- Patent number 10,103,731
- Issue date Oct 16, 2018
- Integrated Silicon Solution, Inc.
- Kim C. Hardee
- G11 - INFORMATION STORAGE
Information Patent Grant
Calibration circuit for on-chip drive and on-die termination
- Patent number 9,780,785
- Issue date Oct 3, 2017
- Integrated Silicon Solution, Inc.
- Kim C. Hardee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dual bit line precharge architecture and method for low power dynam...
- Patent number 8,339,882
- Issue date Dec 25, 2012
- ProMOS Technologies Pte. Ltd.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Short-circuit charge-sharing technique for integrated circuit devices
- Patent number 7,649,406
- Issue date Jan 19, 2010
- United Memories, Inc.
- Michael C. Parris
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Switched capacitor charge sharing technique for integrated circuit...
- Patent number 7,609,570
- Issue date Oct 27, 2009
- United Memories, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Optimized charge sharing for data bus skew applications
- Patent number 7,606,093
- Issue date Oct 20, 2009
- United Memories, Inc.
- Michael C. Parris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Static random access memory (SRAM) compatible, high availability me...
- Patent number 7,506,100
- Issue date Mar 17, 2009
- United Memories, Inc.
- Douglas Blaine Butler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data bus charge-sharing technique for integrated circuit devices
- Patent number 7,463,054
- Issue date Dec 9, 2008
- United Memories, Inc.
- Michael C. Parris
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power-gating system and method for integrated circuit devices
- Patent number 7,372,765
- Issue date May 13, 2008
- United Memories, Inc.
- Kim C. Hardee
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed power-gating technique for integrated circuit devices in...
- Patent number 7,359,277
- Issue date Apr 15, 2008
- United Memories, Inc.
- Kim C. Hardee
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier power-gating technique for integrated circuit memor...
- Patent number 7,248,522
- Issue date Jul 24, 2007
- United Memories, Inc.
- Kim C. Hardee
- G11 - INFORMATION STORAGE
Information Patent Grant
Powergating method and apparatus
- Patent number 7,180,363
- Issue date Feb 20, 2007
- United Memories, Inc.
- Michael C. Parris
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock signal initiated precharge technique for active memory subarr...
- Patent number 7,154,795
- Issue date Dec 26, 2006
- United Memories, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Self-addressed subarray precharge
- Patent number 7,151,711
- Issue date Dec 19, 2006
- United Memories, Inc.
- Kim C. Hardee
- G11 - INFORMATION STORAGE
Information Patent Grant
Powergate control using boosted and negative voltages
- Patent number 7,053,692
- Issue date May 30, 2006
- United Memories, Inc.
- Michael C. Parris
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Column read amplifier power-gating technique for integrated circuit...
- Patent number 6,990,029
- Issue date Jan 24, 2006
- United Memories, Inc.
- Kim C. Hardee
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-contiguous masked refresh for an integrated circuit memory
- Patent number 6,912,168
- Issue date Jun 28, 2005
- United Memories, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Bitline reference voltage circuit
- Patent number 6,788,590
- Issue date Sep 7, 2004
- United Memories, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Optimized read data amplifier and method for operating the same in...
- Patent number 6,738,302
- Issue date May 18, 2004
- United Memories, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
High voltage transistor protection technique and switching circuit...
- Patent number 6,731,156
- Issue date May 4, 2004
- United Memories, Inc.
- Michael C. Parris
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Data bus architecture for integrated circuit devices having embedde...
- Patent number 6,643,160
- Issue date Nov 4, 2003
- United Memories, Inc.
- Kim Carver Hardee
- G11 - INFORMATION STORAGE
Information Patent Grant
Data path decoding technique for an embedded memory array
- Patent number 6,625,069
- Issue date Sep 23, 2003
- United Memories, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Data path decoding technique for an embedded memory array
- Patent number 6,625,066
- Issue date Sep 23, 2003
- United Memories, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Look-ahead refresh for an integrated circuit memory
- Patent number 6,625,078
- Issue date Sep 23, 2003
- United Memories, Inc.
- Oscar Frederick Jones
- G11 - INFORMATION STORAGE
Information Patent Grant
Automatic delay technique for early read and write operations in sy...
- Patent number 6,608,797
- Issue date Aug 19, 2003
- United Memories, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic predecoder circuitry for memory circuits
- Patent number 6,597,201
- Issue date Jul 22, 2003
- Mosel Vitelic, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Switching circuit utilizing a high voltage transistor protection te...
- Patent number 6,580,306
- Issue date Jun 17, 2003
- United Memories, Inc.
- Kim Carver Hardee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Sense amplifier for dynamic random access memory (“DRAM&#x0...
- Patent number 6,552,943
- Issue date Apr 22, 2003
- United Memories, Inc.
- Kim Carver Hardee
- G11 - INFORMATION STORAGE
Information Patent Grant
Small signal, low power read data bus driver for integrated circuit...
- Patent number 6,549,470
- Issue date Apr 15, 2003
- United Memories, Inc.
- Kim Carver Hardee
- G11 - INFORMATION STORAGE
Information Patent Grant
Negative voltage driver circuit technique having reduced current fl...
- Patent number 6,531,900
- Issue date Mar 11, 2003
- United Memories, Inc.
- Kim Carver Hardee
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
CALIBRATION CIRCUIT FOR ON-CHIP DRIVE AND ON-DIE TERMINATION
- Publication number 20180048310
- Publication date Feb 15, 2018
- Integrated Silicon Solution, Inc.
- Kim C. Hardee
- G11 - INFORMATION STORAGE
Information Patent Application
CALIBRATION CIRCUIT FOR ON-CHIP DRIVE AND ON-DIE TERMINATION
- Publication number 20170179953
- Publication date Jun 22, 2017
- Integrated Silicon Solution, Inc.
- Kim C. Hardee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DUAL BIT LINE PRECHARGE ARCHITECTURE AND METHOD FOR LOW POWER DYNAM...
- Publication number 20120008445
- Publication date Jan 12, 2012
- ProMOS Technologies PTE.LTD.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL BIT LINE PRECHARGE ARCHITECTURE AND METHOD FOR LOW POWER DYNAM...
- Publication number 20120008444
- Publication date Jan 12, 2012
- ProMOS Technologies PTE.LTD.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Application
STATIC RANDOM ACCESS MEMORY (SRAM) COMPATIBLE, HIGH AVAILABILITY ME...
- Publication number 20090106488
- Publication date Apr 23, 2009
- United Memories, Inc.
- Douglas Blaine Butler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EARLY WRITE WITH DATA MASKING TECHNIQUE FOR INTEGRATED CIRCUIT DYNA...
- Publication number 20090073786
- Publication date Mar 19, 2009
- United Memories, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Application
SHORT-CIRCUIT CHARGE-SHARING TECHNIQUE FOR INTEGRATED CIRCUIT DEVICES
- Publication number 20090072879
- Publication date Mar 19, 2009
- United Memories, Inc.
- Michael C. Parris
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
OPTIMIZED CHARGE SHARING FOR DATA BUS SKEW APPLICATIONS
- Publication number 20080174340
- Publication date Jul 24, 2008
- United Memories, Inc.
- Michael C. Parris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SWITCHED CAPACITOR CHARGE SHARING TECHNIQUE FOR INTEGRATED CIRCUIT...
- Publication number 20080175074
- Publication date Jul 24, 2008
- United Memories, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Application
Static random access memory (SRAM) compatible, high availability me...
- Publication number 20060190676
- Publication date Aug 24, 2006
- United Memories, Inc. Colorado Springs
- Douglas Blaine Butler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Self-addressed subarray precharge
- Publication number 20060187727
- Publication date Aug 24, 2006
- United Memories, Inc.
- Kim C. Hardee
- G11 - INFORMATION STORAGE
Information Patent Application
Powergating method and apparatus
- Publication number 20060022742
- Publication date Feb 2, 2006
- Michael C. Parris
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clock signal initiated precharge technique for active memory subarr...
- Publication number 20060023530
- Publication date Feb 2, 2006
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Application
Power-gating system and method for integrated circuit devices
- Publication number 20050270074
- Publication date Dec 8, 2005
- United Memories, Inc.
- Kim C. Hardee
- G11 - INFORMATION STORAGE
Information Patent Application
Sense amplifier power-gating technique for integrated circuit memor...
- Publication number 20050052931
- Publication date Mar 10, 2005
- Kim C. Hardee
- G11 - INFORMATION STORAGE
Information Patent Application
Column read amplifier power-gating technique for integrated circuit...
- Publication number 20050052917
- Publication date Mar 10, 2005
- Kim C. Hardee
- G11 - INFORMATION STORAGE
Information Patent Application
High speed power-gating technique for integrated circuit devices in...
- Publication number 20050052936
- Publication date Mar 10, 2005
- Kim C. Hardee
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated circuit transistor body bias regulation circuit and meth...
- Publication number 20050052219
- Publication date Mar 10, 2005
- Douglas Blaine Butler
- G05 - CONTROLLING REGULATING
Information Patent Application
Non-contiguous masked refresh for an integrated circuit memory
- Publication number 20040184334
- Publication date Sep 23, 2004
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Application
BITLINE REFERENCE VOLTAGE CIRCUIT
- Publication number 20040141360
- Publication date Jul 22, 2004
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Application
Powergate control using boosted and negative voltages
- Publication number 20040119529
- Publication date Jun 24, 2004
- Michael C. Parris
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DATA PATH DECODING TECHNIQUE FOR AN EMBEDDED MEMORY ARRAY
- Publication number 20030174542
- Publication date Sep 18, 2003
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Application
DATA PATH DECODING TECHNIQUE FOR AN EMBEDDED MEMORY ARRAY
- Publication number 20030174546
- Publication date Sep 18, 2003
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Application
LOOK-AHEAD REFRESH FOR AN INTEGRATED CIRCUIT MEMORY
- Publication number 20030161207
- Publication date Aug 28, 2003
- Oscar Frederick Jones
- G11 - INFORMATION STORAGE
Information Patent Application
Small signal, low power read data bus driver for integrated circuit...
- Publication number 20020136051
- Publication date Sep 26, 2002
- Kim Carver Hardee
- G11 - INFORMATION STORAGE
Information Patent Application
Negative voltage driver circuit technique having reduced current fl...
- Publication number 20020125918
- Publication date Sep 12, 2002
- Kim Carver Hardee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Switching circuit utilizing a high voltage transistor protection te...
- Publication number 20020125919
- Publication date Sep 12, 2002
- Kim Carver Hardee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Area efficient redundancy multiplexer circuit technique for integra...
- Publication number 20020041198
- Publication date Apr 11, 2002
- Michael Parris
- H03 - BASIC ELECTRONIC CIRCUITRY

Kim C. Hardee

Person

Patents Grantslast 30 patents

Calibration circuit for on-chip drive and on-die termination

Calibration circuit for on-chip drive and on-die termination

Dual bit line precharge architecture and method for low power dynam...

Short-circuit charge-sharing technique for integrated circuit devices

Switched capacitor charge sharing technique for integrated circuit...

Optimized charge sharing for data bus skew applications

Static random access memory (SRAM) compatible, high availability me...

Data bus charge-sharing technique for integrated circuit devices

Power-gating system and method for integrated circuit devices

High speed power-gating technique for integrated circuit devices in...

Sense amplifier power-gating technique for integrated circuit memor...

Powergating method and apparatus

Clock signal initiated precharge technique for active memory subarr...

Self-addressed subarray precharge

Powergate control using boosted and negative voltages

Column read amplifier power-gating technique for integrated circuit...

Non-contiguous masked refresh for an integrated circuit memory

Bitline reference voltage circuit

Optimized read data amplifier and method for operating the same in...

High voltage transistor protection technique and switching circuit...

Data bus architecture for integrated circuit devices having embedde...

Data path decoding technique for an embedded memory array

Data path decoding technique for an embedded memory array

Look-ahead refresh for an integrated circuit memory

Automatic delay technique for early read and write operations in sy...

Dynamic predecoder circuitry for memory circuits

Switching circuit utilizing a high voltage transistor protection te...

Sense amplifier for dynamic random access memory (&#x0201C;DRAM&#x0...

Small signal, low power read data bus driver for integrated circuit...

Negative voltage driver circuit technique having reduced current fl...

Patents Applicationslast 30 patents

CALIBRATION CIRCUIT FOR ON-CHIP DRIVE AND ON-DIE TERMINATION

CALIBRATION CIRCUIT FOR ON-CHIP DRIVE AND ON-DIE TERMINATION

DUAL BIT LINE PRECHARGE ARCHITECTURE AND METHOD FOR LOW POWER DYNAM...

DUAL BIT LINE PRECHARGE ARCHITECTURE AND METHOD FOR LOW POWER DYNAM...

STATIC RANDOM ACCESS MEMORY (SRAM) COMPATIBLE, HIGH AVAILABILITY ME...

EARLY WRITE WITH DATA MASKING TECHNIQUE FOR INTEGRATED CIRCUIT DYNA...

SHORT-CIRCUIT CHARGE-SHARING TECHNIQUE FOR INTEGRATED CIRCUIT DEVICES

OPTIMIZED CHARGE SHARING FOR DATA BUS SKEW APPLICATIONS

SWITCHED CAPACITOR CHARGE SHARING TECHNIQUE FOR INTEGRATED CIRCUIT...

Static random access memory (SRAM) compatible, high availability me...

Self-addressed subarray precharge

Powergating method and apparatus

Clock signal initiated precharge technique for active memory subarr...

Power-gating system and method for integrated circuit devices

Sense amplifier power-gating technique for integrated circuit memor...

Column read amplifier power-gating technique for integrated circuit...

High speed power-gating technique for integrated circuit devices in...

Integrated circuit transistor body bias regulation circuit and meth...

Non-contiguous masked refresh for an integrated circuit memory

BITLINE REFERENCE VOLTAGE CIRCUIT

Powergate control using boosted and negative voltages

DATA PATH DECODING TECHNIQUE FOR AN EMBEDDED MEMORY ARRAY

DATA PATH DECODING TECHNIQUE FOR AN EMBEDDED MEMORY ARRAY

LOOK-AHEAD REFRESH FOR AN INTEGRATED CIRCUIT MEMORY

Small signal, low power read data bus driver for integrated circuit...

Negative voltage driver circuit technique having reduced current fl...

Switching circuit utilizing a high voltage transistor protection te...

Area efficient redundancy multiplexer circuit technique for integra...

Sense amplifier for dynamic random access memory (“DRAM&#x0...