Kiyohito Mukai

Person

Souraku-gun, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor integrated circuit apparatus with low wiring resistance
- Patent number 8,024,689
- Issue date Sep 20, 2011
- Panasonic Corporation
- Noriko Shinomiya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of fabricating a semiconductor device and a method of genera...
- Patent number 7,707,523
- Issue date Apr 27, 2010
- Panasonic Corporation
- Kiyohito Mukai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Area ratio/occupancy ratio verification method and pattern generati...
- Patent number 7,269,807
- Issue date Sep 11, 2007
- Matsushita Electric Industrial Co., Ltd.
- Junichi Shimada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout verification method and method for designing semiconductor i...
- Patent number 7,174,527
- Issue date Feb 6, 2007
- Matsushita Electric Industrial Co., Ltd.
- Masanori Itou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device, method of generating pattern for semiconducto...
- Patent number 7,171,645
- Issue date Jan 30, 2007
- Matsushita Electric Industrial Co., Ltd.
- Mitsumi Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of fabricating a semiconductor device and a method of genera...
- Patent number 7,115,478
- Issue date Oct 3, 2006
- Matsushita Electric Industrial Co., Ltd.
- Kiyohito Mukai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device, method of generating pattern for semiconducto...
- Patent number 7,062,732
- Issue date Jun 13, 2006
- Matsushita Electric Industrial Co., Ltd.
- Mitsumi Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of layout compaction
- Patent number 6,576,147
- Issue date Jun 10, 2003
- Matsushita Electric Industrial Co., Ltd.
- Kiyohito Mukai
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method of layout compaction
- Patent number 6,473,882
- Issue date Oct 29, 2002
- Matsushita Electric Industrial Co., Ltd.
- Kiyohito Mukai
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Mask pattern correction process, photomask and semiconductor integr...
- Patent number 6,303,251
- Issue date Oct 16, 2001
- Matsushita Electric Industrial Co., Ltd.
- Kiyohito Mukai
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Semiconductor device geometrical pattern correction process and geo...
- Patent number 6,183,920
- Issue date Feb 6, 2001
- Matsushita Electric Industrial Co., Ltd.
- Hiroyuki Tsujikawa
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Patents Applicationslast 30 patents

Information Patent Application
METHOD FOR VERIFICATION OF MASK LAYOUT OF SEMICONDUCTOR INTEGRATED...
- Publication number 20100242011
- Publication date Sep 23, 2010
- Kiyohito Mukai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RELIABILITY DESIGN METHOD
- Publication number 20080209367
- Publication date Aug 28, 2008
- Kiyohito MUKAI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor integrated circuit, and method and apparatus for desi...
- Publication number 20070272949
- Publication date Nov 29, 2007
- Noriko Shinomiya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE LAYOUT INSPECTION METHOD
- Publication number 20070136702
- Publication date Jun 14, 2007
- Matsushita Electric Industrial Co., Ltd.
- Kiyohito MUKAI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of fabricating a semiconductor device and a method of genera...
- Publication number 20070020880
- Publication date Jan 25, 2007
- Matsushita Electric Industrial Co., Ltd.
- Kiyohito Mukai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor integrated circuit and method for manufacturing semic...
- Publication number 20060197573
- Publication date Sep 7, 2006
- Yoichi Matsumura
- G01 - MEASURING TESTING
Information Patent Application
Layout verification method and method for designing semiconductor i...
- Publication number 20060115911
- Publication date Jun 1, 2006
- MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- Masanori Itou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor integrated circuit device, method of enerating patter...
- Publication number 20050224914
- Publication date Oct 13, 2005
- MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- Kiyohito Mukai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Layout data verification method, mask pattern verification method a...
- Publication number 20050204327
- Publication date Sep 15, 2005
- MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- Kiyohito Mukai
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Area ratio/occupancy ratio verification method and pattern generati...
- Publication number 20050172248
- Publication date Aug 4, 2005
- MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- Junichi Shimada
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor device layout inspection method
- Publication number 20040139407
- Publication date Jul 15, 2004
- Kiyohito Mukai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor device, method of generating pattern for semiconducto...
- Publication number 20040139412
- Publication date Jul 15, 2004
- Mitsumi Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor device, method of generating pattern for semiconducto...
- Publication number 20040102034
- Publication date May 27, 2004
- Mitsumi Ito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of fabricating a semiconductor device and a method of genera...
- Publication number 20040083445
- Publication date Apr 29, 2004
- MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- Kiyohito Mukai
- G06 - COMPUTING CALCULATING COUNTING

Kiyohito Mukai

Person

Patents Grantslast 30 patents

Semiconductor integrated circuit apparatus with low wiring resistance

Method of fabricating a semiconductor device and a method of genera...

Area ratio/occupancy ratio verification method and pattern generati...

Layout verification method and method for designing semiconductor i...

Semiconductor device, method of generating pattern for semiconducto...

Method of fabricating a semiconductor device and a method of genera...

Semiconductor device, method of generating pattern for semiconducto...

Method of layout compaction

Method of layout compaction

Mask pattern correction process, photomask and semiconductor integr...

Semiconductor device geometrical pattern correction process and geo...

Patents Applicationslast 30 patents

METHOD FOR VERIFICATION OF MASK LAYOUT OF SEMICONDUCTOR INTEGRATED...

RELIABILITY DESIGN METHOD

Semiconductor integrated circuit, and method and apparatus for desi...

SEMICONDUCTOR DEVICE LAYOUT INSPECTION METHOD

Method of fabricating a semiconductor device and a method of genera...

Semiconductor integrated circuit and method for manufacturing semic...

Layout verification method and method for designing semiconductor i...

Semiconductor integrated circuit device, method of enerating patter...

Layout data verification method, mask pattern verification method a...

Area ratio/occupancy ratio verification method and pattern generati...

Semiconductor device layout inspection method

Semiconductor device, method of generating pattern for semiconducto...

Semiconductor device, method of generating pattern for semiconducto...

Method of fabricating a semiconductor device and a method of genera...