Kwun-Yao Ho

Person

Taipei Hsien, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Optical unit
- Patent number 11,997,793
- Issue date May 28, 2024
- Nidec Corporation
- Shinri Ono
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Optical unit
- Patent number 11,627,663
- Issue date Apr 11, 2023
- Nidec Corporation
- Soichiro Kimura
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Multi-chip package
- Patent number 8,269,329
- Issue date Sep 18, 2012
- Via Technologies, Inc.
- Moriss Kung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip package
- Patent number 7,638,881
- Issue date Dec 29, 2009
- VIA Technologies, Inc.
- Chia-Jung Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Manufacturing process of a chip package structure
- Patent number 7,622,326
- Issue date Nov 24, 2009
- VIA Technologies, Inc.
- Kwun-Yao Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip and manufacturing method and application thereof
- Patent number 7,504,726
- Issue date Mar 17, 2009
- VIA Technologies, Inc.
- Kwun-Yao Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-conducting through hole structure
- Patent number 7,470,864
- Issue date Dec 30, 2008
- VIA Technologies, Inc.
- Kwun-Yao Ho
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Chip package and bump connecting structure thereof
- Patent number 7,382,049
- Issue date Jun 3, 2008
- VIA Technologies, Inc.
- Kwun-Yao Ho
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Low coefficient of thermal expansion build-up layer packaging and m...
- Patent number 7,342,317
- Issue date Mar 11, 2008
- Via Technologies, Inc.
- Kwun-Yao Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip carrier with oxidation protection layer
- Patent number 7,247,951
- Issue date Jul 24, 2007
- VIA Technologies, Inc.
- Kwun-Yao Ho
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Conductive block mounting process for electrical connection
- Patent number 7,235,429
- Issue date Jun 26, 2007
- VIA Technologies, Inc.
- Kwun-Yao Ho
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Stacked multi-chip package
- Patent number 7,180,166
- Issue date Feb 20, 2007
- Via Technologies, Inc.
- Kwun-Yao Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit package with a balanced-part structure
- Patent number 7,176,559
- Issue date Feb 13, 2007
- VIA Technologies, Inc.
- Kwun Yao Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High performance thermally enhanced package and method of fabricati...
- Patent number 7,173,341
- Issue date Feb 6, 2007
- VIA Technologies, Inc.
- Kwun-Yao Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrical package capable of increasing the density of bonding pad...
- Patent number 7,071,569
- Issue date Jul 4, 2006
- VIA Technologies, Inc.
- Kwun-Yao Ho
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Packaging substrate without plating bar and a method of forming the...
- Patent number 7,033,917
- Issue date Apr 25, 2006
- VIA Technologies, Inc.
- Kwun-Yao Ho
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Circuit board and fabricating process thereof
- Patent number 6,981,320
- Issue date Jan 3, 2006
- VIA Technologies, Inc.
- Kwun-Yao Ho
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
High density laminated substrate structure and manufacture method t...
- Patent number 6,977,348
- Issue date Dec 20, 2005
- VIA Technologies, Inc.
- Kwun-Yao Ho
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Module board having embedded chips and components and method of for...
- Patent number 6,972,964
- Issue date Dec 6, 2005
- Via Technologies Inc.
- Kwun-Yao Ho
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Multi-chip package and manufacturing method thereof
- Patent number 6,960,826
- Issue date Nov 1, 2005
- VIA Technologies, Inc.
- Kwun-Yao Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip packaging structure and manufacturing process thereof
- Patent number 6,951,773
- Issue date Oct 4, 2005
- VIA Technologies, Inc.
- Kwun-Yo Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical routing structure
- Patent number 6,946,727
- Issue date Sep 20, 2005
- VIA Technologies, Inc.
- Kwun-Yao Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrical connection device between a pin-typed IC package and a c...
- Patent number 6,929,488
- Issue date Aug 16, 2005
- VIA Technologies, Inc.
- Moriss Kung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bump process for flip chip package
- Patent number 6,916,687
- Issue date Jul 12, 2005
- VIA Technologies, Inc.
- Kwun-Yao Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lamination process and structure of high layout density substrate
- Patent number 6,913,814
- Issue date Jul 5, 2005
- VIA Technologies, Inc.
- Kwun-Yao Ho
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Process of forming bonding columns
- Patent number 6,902,997
- Issue date Jun 7, 2005
- VIA Technologies, Inc.
- Kwun-Yao Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating circuit substrate
- Patent number 6,896,173
- Issue date May 24, 2005
- VIA Technologies, Inc.
- Kwun-Yao Ho
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Tab package
- Patent number 6,894,904
- Issue date May 17, 2005
- VIA Technologies, Inc.
- Moriss Kung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chip scale package with heat dissipating part
- Patent number 6,876,087
- Issue date Apr 5, 2005
- VIA Technologies, Inc.
- Kwun-Yao Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Module board having embedded chips and components and method of for...
- Patent number 6,865,089
- Issue date Mar 8, 2005
- VIA Technologies, Inc.
- Kwun-Yao Ho
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
COMPOSITE TWO-PHASE FLUID COOLING MOTOR AND COMPOSITE TWO-PHASE FLU...
- Publication number 20240322651
- Publication date Sep 26, 2024
- TECO Electric & Machinery Co., Ltd.
- Kwun-Yao HO
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
COOLING DEVICE
- Publication number 20240049430
- Publication date Feb 8, 2024
- NIDEC CORPORATION
- Tsung-Ting HSIEH
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
HEAT DISSIPATION MEMBER AND COOLING DEVICE
- Publication number 20220352051
- Publication date Nov 3, 2022
- NIDEC CORPORATION
- Tsungting HSIEH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Light-emitting semiconductor packaging structure without wire bonding
- Publication number 20100084673
- Publication date Apr 8, 2010
- Kwun-Yao HO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Flat-plate loop heat conduction device and manufacturing method the...
- Publication number 20100044014
- Publication date Feb 25, 2010
- Kwun-Yao Ho
- F28 - HEAT EXCHANGE IN GENERAL
Information Patent Application
ELECTRONIC APPARATUS
- Publication number 20090296330
- Publication date Dec 3, 2009
- VIA TECHNOLOGIES, INC.
- Kwun-Yao Ho
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-chip package
- Publication number 20090200651
- Publication date Aug 13, 2009
- VIA TECHNOLOGIES, INC.
- Moriss Kung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP AND MANUFACTURING METHOD AND APPLICATION THEREOF
- Publication number 20080122077
- Publication date May 29, 2008
- VIA TECHNOLOGIES, INC.
- Kwun-Yao Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTRONIC APPARATUS
- Publication number 20080084677
- Publication date Apr 10, 2008
- VIA TECHNOLOGIES, INC.
- Chih-Long Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Chip package and fabricating method thereof
- Publication number 20070222072
- Publication date Sep 27, 2007
- Chia-Jung Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor package and fabricating method thereof
- Publication number 20070164447
- Publication date Jul 19, 2007
- Kwun-Yao Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Bumpless chip package and fabricating process thereof
- Publication number 20070069352
- Publication date Mar 29, 2007
- Kwun-Yao Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Chip package and bump connecting structure thereof
- Publication number 20070045869
- Publication date Mar 1, 2007
- Kwun-Yao Ho
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
MANUFACTURING PROCESS OF A CHIP PACKAGE STRUCTURE
- Publication number 20060231863
- Publication date Oct 19, 2006
- KWUN-YAO HO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Flip chip package and the fabrication thereof
- Publication number 20060220245
- Publication date Oct 5, 2006
- Kwun-Yao Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Assembly structure and method for embedded passive device
- Publication number 20060118931
- Publication date Jun 8, 2006
- Kwun-Yao Ho
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Cavity-down stacked multi-chip package
- Publication number 20060071314
- Publication date Apr 6, 2006
- Via Technologies, Inc.
- Kwun-Yao Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Chip carrier and chip package structure thereof
- Publication number 20060055023
- Publication date Mar 16, 2006
- Kwun-Yao Ho
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Multi-conducting through hole structure
- Publication number 20060012030
- Publication date Jan 19, 2006
- Kwun-Yao Ho
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Packaging substrate without plating bar and a method of forming the...
- Publication number 20050266608
- Publication date Dec 1, 2005
- Via Technologies, Inc.
- Kwun-Yao Ho
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Fine-pitch packaging substrate and a method of forming the same
- Publication number 20050258551
- Publication date Nov 24, 2005
- Via Technologies, Inc.
- Kwun-Yao Ho
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Stacked multi-chip package
- Publication number 20050253224
- Publication date Nov 17, 2005
- Via Technologies, Inc.
- Kwun-Yao Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHIP PACKAGING STRUCTURE
- Publication number 20050230797
- Publication date Oct 20, 2005
- Kwun-Yo Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process of plating through hole
- Publication number 20050196898
- Publication date Sep 8, 2005
- Kwun-Yao Ho
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Low coefficient of thermal expansion build-up layer packaging and m...
- Publication number 20050189644
- Publication date Sep 1, 2005
- Kwun-Yao Ho
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Module board having embedded chips and components and method of for...
- Publication number 20050122698
- Publication date Jun 9, 2005
- VIA TECHNOLOGIES INC.
- Kwun-Yao Ho
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Bump transfer fixture
- Publication number 20050035453
- Publication date Feb 17, 2005
- Kwun-Yao Ho
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
[ELECTRICAL PACKAGE AND MANUFACTURING METHOD THEREOF]
- Publication number 20050035464
- Publication date Feb 17, 2005
- Kwun-Yao Ho
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
[MULTI-CHIP PACKAGE AND MANUFACTURING METHOD THEREOF]
- Publication number 20050029644
- Publication date Feb 10, 2005
- KWUN-YAO HO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Conductive block mounting process for electrical connection
- Publication number 20050026330
- Publication date Feb 3, 2005
- Kwun-Yao Ho
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR

Kwun-Yao Ho

Person

Patents Grantslast 30 patents

Optical unit

Optical unit

Multi-chip package

Chip package

Manufacturing process of a chip package structure

Chip and manufacturing method and application thereof

Multi-conducting through hole structure

Chip package and bump connecting structure thereof

Low coefficient of thermal expansion build-up layer packaging and m...

Chip carrier with oxidation protection layer

Conductive block mounting process for electrical connection

Stacked multi-chip package

Integrated circuit package with a balanced-part structure

High performance thermally enhanced package and method of fabricati...

Electrical package capable of increasing the density of bonding pad...

Packaging substrate without plating bar and a method of forming the...

Circuit board and fabricating process thereof

High density laminated substrate structure and manufacture method t...

Module board having embedded chips and components and method of for...

Multi-chip package and manufacturing method thereof

Chip packaging structure and manufacturing process thereof

Vertical routing structure

Electrical connection device between a pin-typed IC package and a c...

Bump process for flip chip package

Lamination process and structure of high layout density substrate

Process of forming bonding columns

Method of fabricating circuit substrate

Tab package

Chip scale package with heat dissipating part

Module board having embedded chips and components and method of for...

Patents Applicationslast 30 patents

COMPOSITE TWO-PHASE FLUID COOLING MOTOR AND COMPOSITE TWO-PHASE FLU...

COOLING DEVICE

HEAT DISSIPATION MEMBER AND COOLING DEVICE

Light-emitting semiconductor packaging structure without wire bonding

Flat-plate loop heat conduction device and manufacturing method the...

ELECTRONIC APPARATUS

Multi-chip package

CHIP AND MANUFACTURING METHOD AND APPLICATION THEREOF

ELECTRONIC APPARATUS

Chip package and fabricating method thereof

Semiconductor package and fabricating method thereof

Bumpless chip package and fabricating process thereof

Chip package and bump connecting structure thereof

MANUFACTURING PROCESS OF A CHIP PACKAGE STRUCTURE

Flip chip package and the fabrication thereof

Assembly structure and method for embedded passive device

Cavity-down stacked multi-chip package

Chip carrier and chip package structure thereof

Multi-conducting through hole structure

Packaging substrate without plating bar and a method of forming the...

Fine-pitch packaging substrate and a method of forming the same

Stacked multi-chip package

CHIP PACKAGING STRUCTURE

Process of plating through hole

Low coefficient of thermal expansion build-up layer packaging and m...

Module board having embedded chips and components and method of for...

Bump transfer fixture

[ELECTRICAL PACKAGE AND MANUFACTURING METHOD THEREOF]

[MULTI-CHIP PACKAGE AND MANUFACTURING METHOD THEREOF]

Conductive block mounting process for electrical connection