This application claims the priority benefit of Taiwan application serial no. 94133509, filed on Sep. 27, 2005. All disclosure of the Taiwan application is incorporated herein by reference.
1. Field of Invention
The present invention relates to a chip package and the fabricating process thereof, and more particularly to a bumpless chip package and the fabricating process thereof.
2. Description of Related Art
With the constant improvement of electronic technologies every day, in order to meet various demands on electronic components such as high-speed processing, multi-function, integration, miniature, light weight and low prices, the development of chip package technology also tends to move towards miniaturization and high density. Conventional ball grid array (BGA) package technology often employs a package substrate as the carrier of the integrated circuit (IC) chip, electrically connects the chip to the top surface of the package substrate by the electrical connection techniques such as flip chip bonding or wire bonding, and then disposes a plurality of solder balls on the bottom surface of the package substrate in area array. Therefore, the chip can be electrically connected to the electronic device of the next level, for example, the Printed Circuit Board, via the inner circuit of the package substrate and a plurality of solder balls on the bottom thereof.
However, the conventional BGA package technology has to use the package substrate of high layout density, in combination with the electrical connection techniques such as flip chip bonding or wire bonding, thus resulting in a rather long signal transmission path. Therefore, a chip package technology of bumpless build-up layer (BBUL) has been developed recently, wherein the fabricating process of flip chip bonding or wire bonding is omitted, and a multi-layered interconnection structure is made directly on the chip, and the electrical contacts such as solder balls or pins are fabricated on the multi-layered interconnection structure in area array to be electrically connected to the electronic device of the next level.
Referring to
The interconnection structure 140 is formed on the active surface 124 of the chip 120 and the supporting surface 112 of the heat spreader 110, wherein the interconnection structure 140 has an inner circuit 142 and a plurality of contact pads 144. The contact pads 144 are formed on a contact surface 146 of the interconnection structure 140. At least one of the chip pads 122 is electrically connected with at least one of the contact pads 144 by the inner circuit 142.
Additionally, the interconnection structure 140 comprises a plurality of dielectric layers 148, a plurality of conductive vias 142a and a plurality of circuit layers 142b. The conductive vias 142a and the circuit layers 142b form the inner circuit 142 described above. In particular, at least one of the conductive vias 142a is electrically connected with at least one of the chip pads 122. The conductive vias 142a run through the dielectric layers 148 respectively, and the dielectric layers 148 and the circuit layers 142b are formed alternately with each other. It can be known from
However, since the thermal conductivity of the dielectric material located between the chip 120 and the cavity 114 is poor, the heat caused during the operation of the chip 120 is conducted to the heat spreader 110 mainly by the thermal-conductive adhesion layer 130 located at the back surface of the chip 120, thus the overall heat dissipation of the conventional bumpless chip package 100 is poor. Moreover, it is not easy to fill the dielectric material described above into space S between the sides of the chip 120 and the side walls of the cavity 114. Furthermore, since the coefficient of thermal expansion (CTE) of the dielectric material described above does not match with the coefficients of thermal expansion of the heat spreader 110 and the chip 120, the thermal stress may remain in the dielectric material. As described above, it is indeed necessary to improve the conventional bumpless chip package 100.
The present invention provides a bumpless chip package comprising a supporting component, a chip, a metal-filled layer and an interconnection structure. The supporting component has a supporting surface and a cavity. The chip is disposed within the cavity, and the chip has a plurality of chip pads formed on an active surface of the chip, wherein the active surface is upward. Moreover, the metal-filled layer is filled in a space formed between the chip and the cavity. Additionally, the interconnection structure is formed above the active surface of the chip and the supporting surface of the supporting component and has an inner circuit and a plurality of contact pads. The contact pads are formed on a contact surface of the interconnection structure. At least one of the chip pads is electrically connected with at least one of the contact pads by the inner circuit.
The present invention further provides a fabricating process of the bumpless chip package. A supporting component having a supporting surface and a cavity is provided. A chip having a plurality of chip pads formed on an active surface of the chip is provided. The chip is disposed within the cavity, wherein the active surface is upward. A metal-filled layer in a space formed between the chip and the cavity is formed. An interconnection structure above the active surface of the chip and the supporting surface of the supporting component is formed. The interconnection structure has an inner circuit and a plurality of contact pads. The contact pads are formed on the contact surface of the interconnection structure. At least one of the chip pads is electrically connected with at least one of the contact pads by the inner circuit.
In order to make the aforementioned features and advantages of the present invention more comprehensible, preferred embodiments accompanied with appended drawings are described in detail below.
Then, a chip 220 is provided. The chip 220 has a plurality of chip pads 222 which are formed on an active surface 224 of the chip 220. In the embodiment, the chip 220 further has a protection layer P, which is formed on the active surface 224 and exposes each of the chip pads 222. The protection layer P is used to protect the inner circuit (not shown in
Then, referring to
Further, referring to
In the embodiment, the metal-filled layer 230 uses metal material, for example, elemental metal or alloy metal, which has excellent characteristics of thermal conductivity. Therefore the thermal conductive efficiency between the chip 220 and the supporting component 210 can be increased. Furthermore, the coefficient of thermal expansion of the supporting component 210 can be set the same as or similar to the coefficient of expansion of the metal-filled layer 230, therefore the mismatch between the thermal expansion of the chip 220 and the supporting component 210 can be reduced so as to decrease the remaining of the thermal stress.
Referring to
The formation of the patterned metal layer M as described above may include a first step of forming a metal layer (not shown in
Referring to
The interconnection structure 240 described above, for example, is formed on the patterned metal layer M by a build-up process. In particular, the dielectric layer 248, at least one conductive via 242a running through the dielectric layer 248, and the circuit layers 242b electrically connected with the conductive vias 242a are sequentially formed on the patterned metal layer M. The interconnection structure 240 can be formed by conducting the above steps once or more times according to the requirements of design. In the embodiment, the interconnection structure 240, for example, comprises a plurality of dielectric layers 248, a plurality of conductive vias 242a and a plurality of circuit layers 242b, wherein the conductive vias 242a and the circuit layers 242b form the inner circuit 242. It can be known from
Referring to
It should be mentioned that the contact pads 244 can be used for the signal I/O interfaces of land grid array (LGA) type, if a plurality of electrical contacts 250 have not been respectively disposed on the contact pads 244. If the electrical contacts 250 are conductive balls, they can be used to provide the signal I/O interfaces of ball grid array (BGA) type. If the electrical contacts 250 are conductive pins, they can be used to provide the signal I/O interfaces of pin grid array (PGA) type. If the electrical contacts 250 are conductive columns, they can be used to provide the signal I/O interfaces of column grid array (CGA) type.
Referring to
To sum up, the bumpless chip package and the fabricating process thereof according to the present invention have the following advantages:
(a) Since the material of the metal-filled layer filled between the chip and the cavity according to the present invention is metal, the metal-filled layer can increase the thermal conductive efficiency between the chip and the supporting component;
(b) Since the metal-filled layer of the present invention can be filled and formed between the chip and the cavity by electroplating, sputtering or metal deposition and so on, the metal-filled layer is more easily filled between the chin and the cavity compared with the conventional technology;
(c) Since the coefficient of thermal expansion of the metal-filled layer according to the present invention is similar to the coefficients of thermal expansion of the chip and the supporting component, the mismatch between the thermal expansion of the metal-filled layer of the present invention and those of the chip and the supporting component can be reduced so as to decrease the remaining of the thermal stress.
Although the present invention is disclosed as above by preferred embodiments, they are not intended to limit the present invention. Various variations and modifications can be made by those skilled in the art without departing from the spirit and scope of the present invention, and the scope of the present invention shall be defined by the appended claims.
Number | Date | Country | Kind |
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94133509 | Sep 2005 | TW | national |