Loi Nguyen

Person

Carrollton, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Embedded microelectromechanical systems (MEMS) semiconductor substr...
- Patent number RE45286
- Issue date Dec 9, 2014
- STMicroelectronics, Inc.
- Olivier Le Neel
- 438 - Semiconductor device manufacturing: process
Information Patent Grant
MEMS packaging scheme using dielectric fence
- Patent number 8,853,850
- Issue date Oct 7, 2014
- STMicroelectronics, Inc.
- Venkatesh Mohanakrishnaswamy
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Method of forming a die having an IC region adjacent a MEMS region
- Patent number 8,853,802
- Issue date Oct 7, 2014
- STMicroelectronics, Inc.
- Venkatesh Mohanakrishnaswamy
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
High aspect ratio capacitively coupled MEMS devices
- Patent number 8,680,631
- Issue date Mar 25, 2014
- STMicroelectronics, Inc.
- Venkatesh Mohanakrishnaswamy
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
High aspect ratio capacitively coupled MEMS devices
- Patent number 8,432,006
- Issue date Apr 30, 2013
- STMicroelectronics, Inc.
- Venkatesh Mohanakrishnaswamy
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
MEMS packaging scheme using dielectric fence
- Patent number 8,405,202
- Issue date Mar 26, 2013
- STMicroelectronics, Inc.
- Venkatesh Mohanakrishnaswamy
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Method of forming a die having an IC region adjacent a MEMS region
- Patent number 8,193,595
- Issue date Jun 5, 2012
- STMicroelectronics, Inc.
- Venkatesh Mohanakrishnaswamy
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
High aspect ratio all SiGe capacitively coupled MEMS devices
- Patent number 8,022,491
- Issue date Sep 20, 2011
- STMicroelectronics, Inc.
- Venkatesh Mohanakrishnaswamy
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Embedded microelectromechanical systems (MEMS) semiconductor substr...
- Patent number 7,943,410
- Issue date May 17, 2011
- STMicroelectronics, Inc.
- Olivier Le Neel
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
Sram cell fabrication with interlevel Dielectric planarization
- Patent number RE41670
- Issue date Sep 14, 2010
- STMicroelectronics, Inc.
- Loi Nguyen
- 257 - Active solid-state devices
Information Patent Grant
Method and interlevel dielectric structure for improved metal step...
- Patent number 6,812,142
- Issue date Nov 2, 2004
- STMicroelectronics, Inc.
- Loi Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory masking for periphery salicidation of active regions
- Patent number 6,661,064
- Issue date Dec 9, 2003
- STMicroelectronics, Inc.
- Robert Louis Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
EEPROM memory cell with increased dielectric integrity
- Patent number 6,518,620
- Issue date Feb 11, 2003
- STMicroelectronics, Inc.
- Tsiu Chiu Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for memory masking for periphery salicidation of active regions
- Patent number 6,514,811
- Issue date Feb 4, 2003
- STMicroelectronics, Inc.
- Robert Louis Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming an integrated circuit contact structure having ga...
- Patent number 6,472,261
- Issue date Oct 29, 2002
- STMicroelectronics, Inc.
- Loi N. Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of masking for periphery salicidation of active regions
- Patent number 6,284,584
- Issue date Sep 4, 2001
- STMicroelectronics, Inc.
- Robert Louis Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making an SRAM storage cell with N channel thin film tran...
- Patent number 6,251,713
- Issue date Jun 26, 2001
- STMicroelectronics, Inc.
- Tsiu Chiu Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of forming a landing pad structure in an integrated circuit
- Patent number RE36938
- Issue date Oct 31, 2000
- STMicroelectronics, Inc.
- Tsiu C. Chan
- 438 - Semiconductor device manufacturing: process
Information Patent Grant
Method of fabricating an integrated circuit
- Patent number 6,107,194
- Issue date Aug 22, 2000
- STMicroelectronics, Inc.
- Robert Louis Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of patterning a submicron semiconductor layer
- Patent number 6,096,634
- Issue date Aug 1, 2000
- STMicroelectronics, Inc.
- Loi Ngoc Nguyen
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Dual landing pad structure including dielectric pocket
- Patent number 6,093,963
- Issue date Jul 25, 2000
- STMicroelectronics, Inc.
- Tsiu C. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit contact structure having gate electrode protecti...
- Patent number 6,057,604
- Issue date May 2, 2000
- STMicroelectronics, Inc.
- Loi N. Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory masking for periphery salicidation of active regions
- Patent number 6,051,864
- Issue date Apr 18, 2000
- STMicroelectronics, Inc.
- Robert Louis Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a metal contact to landing pad structure in an in...
- Patent number 5,956,615
- Issue date Sep 21, 1999
- STMicroelectronics, Inc.
- Loi N. Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual landing pad structure in an integrated circuit
- Patent number 5,945,738
- Issue date Aug 31, 1999
- STMicroelectronics, Inc.
- Loi N. Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a metal contact to landing pad structure in an in...
- Patent number 5,914,518
- Issue date Jun 22, 1999
- STMicroelectronics, Inc.
- Loi N. Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a landing pad structure in an integrated circuit
- Patent number 5,909,636
- Issue date Jun 1, 1999
- STMicroelectronics, Inc.
- Loi N. Nguyen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a landing pad structure in an integrated circuit
- Patent number 5,894,160
- Issue date Apr 13, 1999
- STMicroelectronics, Inc.
- Tsiu C. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making EEPROM cell structure
- Patent number 5,885,871
- Issue date Mar 23, 1999
- STMicrolelectronics, Inc.
- Tsiu Chiu Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making and structure of SRAM storage cell with N channel...
- Patent number 5,870,330
- Issue date Feb 9, 1999
- STMicroelectronics, Inc.
- Tsiu Chiu Chan
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMS PACKAGING SCHEME USING DIELECTRIC FENCE
- Publication number 20140061824
- Publication date Mar 6, 2014
- STMicroelectronics, Inc.
- Venkatesh Mohanakrishnaswamy
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
HIGH ASPECT RATIO CAPACITIVELY COUPLED MEMS DEVICES
- Publication number 20130228881
- Publication date Sep 5, 2013
- STMicroelectronics, Inc.
- Venkatesh Mohanakrishnaswamy
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
METHOD OF FORMING A DIE HAVING AN IC REGION ADJACENT A MEMS REGION
- Publication number 20120235254
- Publication date Sep 20, 2012
- STMICROELECTRONICS ASIA PACIFIC PTE, LTD.
- Venkatesh Mohanakrishnaswamy
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
HIGH ASPECT RATIO CAPACITIVELY COUPLED MEMS DEVICES
- Publication number 20120056281
- Publication date Mar 8, 2012
- STMicroelectronics, Inc.
- Venkatesh Mohanakrishnaswamy
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
METHOD OF FORMING A DIE HAVING AN IC REGION ADJACENT A MEMS REGION
- Publication number 20110156175
- Publication date Jun 30, 2011
- STMicroelectronics, Inc.
- Venkatesh Mohanakrishnaswamy
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
MEMS PACKAGING SCHEME USING DIELECTRIC FENCE
- Publication number 20110042801
- Publication date Feb 24, 2011
- STMicroelectronics, Inc.
- Venkatesh Mohanakrishnaswamy
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
HIGH ASPECT RATIO ALL SIGE CAPACITIVELY COUPLED MEMS DEVICES
- Publication number 20100164024
- Publication date Jul 1, 2010
- STMicroelectronics, Inc.
- Venkatesh Mohanakrishnaswamy
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
EMBEDDED MICROELECTROMECHANICAL SYSTEMS (MEMS) SEMICONDUCTOR SUBSTR...
- Publication number 20100140724
- Publication date Jun 10, 2010
- STMicroelectronics, Inc.
- Olivier LE NEEL
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
MEMORY MASKING FOR PERIPHERY SALICIDATION OF ACTIVE REGIONS
- Publication number 20030190781
- Publication date Oct 9, 2003
- SGS-Thomson Microelectronics, Inc.
- Robert Louis Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory masking for periphery salicidation of active regions
- Publication number 20020020889
- Publication date Feb 21, 2002
- Robert Louis Hodges
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING AN INTEGRATED CIRCUIT CONTACT STRUCTURE HAVING GA...
- Publication number 20020000627
- Publication date Jan 3, 2002
- LOI N. NGUYEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EEPROM MEMORY CELL WITH INCREASED DIELECTRIC INTEGRITY
- Publication number 20010022377
- Publication date Sep 20, 2001
- TSIU CHIU CHAN
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Embedded microelectromechanical systems (MEMS) semiconductor substr...

MEMS packaging scheme using dielectric fence

Method of forming a die having an IC region adjacent a MEMS region

High aspect ratio capacitively coupled MEMS devices

High aspect ratio capacitively coupled MEMS devices

MEMS packaging scheme using dielectric fence

Method of forming a die having an IC region adjacent a MEMS region

High aspect ratio all SiGe capacitively coupled MEMS devices

Embedded microelectromechanical systems (MEMS) semiconductor substr...

Sram cell fabrication with interlevel Dielectric planarization

Method and interlevel dielectric structure for improved metal step...

Memory masking for periphery salicidation of active regions

EEPROM memory cell with increased dielectric integrity

Method for memory masking for periphery salicidation of active regions

Method of forming an integrated circuit contact structure having ga...

Method of masking for periphery salicidation of active regions

Method of making an SRAM storage cell with N channel thin film tran...

Method of forming a landing pad structure in an integrated circuit

Method of fabricating an integrated circuit

Method of patterning a submicron semiconductor layer

Dual landing pad structure including dielectric pocket

Integrated circuit contact structure having gate electrode protecti...

Memory masking for periphery salicidation of active regions

Method of forming a metal contact to landing pad structure in an in...

Dual landing pad structure in an integrated circuit

Method of forming a metal contact to landing pad structure in an in...

Method of forming a landing pad structure in an integrated circuit

Method of forming a landing pad structure in an integrated circuit

Method of making EEPROM cell structure

Method of making and structure of SRAM storage cell with N channel...

Patents Applicationslast 30 patents

MEMS PACKAGING SCHEME USING DIELECTRIC FENCE

HIGH ASPECT RATIO CAPACITIVELY COUPLED MEMS DEVICES

METHOD OF FORMING A DIE HAVING AN IC REGION ADJACENT A MEMS REGION

HIGH ASPECT RATIO CAPACITIVELY COUPLED MEMS DEVICES

METHOD OF FORMING A DIE HAVING AN IC REGION ADJACENT A MEMS REGION

MEMS PACKAGING SCHEME USING DIELECTRIC FENCE

HIGH ASPECT RATIO ALL SIGE CAPACITIVELY COUPLED MEMS DEVICES

EMBEDDED MICROELECTROMECHANICAL SYSTEMS (MEMS) SEMICONDUCTOR SUBSTR...

MEMORY MASKING FOR PERIPHERY SALICIDATION OF ACTIVE REGIONS

Memory masking for periphery salicidation of active regions

METHOD OF FORMING AN INTEGRATED CIRCUIT CONTACT STRUCTURE HAVING GA...

EEPROM MEMORY CELL WITH INCREASED DIELECTRIC INTEGRITY