Lynne A. Okada

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method for forming inlaid structures for IC interconnections
- Patent number 7,279,410
- Issue date Oct 9, 2007
- Advanced Micro Devices, Inc.
- Lynne A. Okada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ultra low dielectric constant integrated circuit system
- Patent number 7,256,499
- Issue date Aug 14, 2007
- Advanced Micro Devices, Inc.
- Lu You
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sealing sidewall pores in low-k dielectrics
- Patent number 7,208,418
- Issue date Apr 24, 2007
- Advanced Micro Devices, Inc.
- Lynne A. Okada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect with multiple layers of conductive material with grain...
- Patent number 7,001,840
- Issue date Feb 21, 2006
- Advanced Micro Devices, Inc.
- Minh Quoc Tran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for reworking a multi-layer photoresist following an underla...
- Patent number 6,872,663
- Issue date Mar 29, 2005
- Advanced Micro Devices, Inc.
- Lynne A. Okada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
N-containing plasma etch process with reduced resist poisoning
- Patent number 6,846,749
- Issue date Jan 25, 2005
- Advanced Micro Devices, Inc.
- Calvin T. Gabriel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming dual inlaid structures for IC interconnections
- Patent number 6,767,827
- Issue date Jul 27, 2004
- Advanced Micro Devices, Inc.
- Lynne A. Okada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming dual damascene interconnect structure
- Patent number 6,756,300
- Issue date Jun 29, 2004
- Advanced Micro Devices, Inc.
- Fei Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vapor treatment for repairing damage of low-k dielectric
- Patent number 6,713,382
- Issue date Mar 30, 2004
- Advanced Micro Devices, Inc.
- Suzette K. Pangrle
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Polymer spacers for creating small geometry space and method of man...
- Patent number 6,699,792
- Issue date Mar 2, 2004
- Advanced Micro Devices, Inc.
- Fei Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual damascene metal interconnect structure with dielectric studs
- Patent number 6,660,619
- Issue date Dec 9, 2003
- Advanced Micro Devices, Inc.
- Suzette K. Pangrle
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual damascene with silicon carbide middle etch stop layer/ARC
- Patent number 6,656,830
- Issue date Dec 2, 2003
- Advanced Micro Devices, Inc.
- Ramkumar Subramanian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming an interconnect structure using a CVD organic BA...
- Patent number 6,632,707
- Issue date Oct 14, 2003
- Advanced Micro Devices, Inc.
- Fei Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Plasma etching using combination of CHF3 and CH3F
- Patent number 6,610,608
- Issue date Aug 26, 2003
- Advanced Micro Devices, Inc.
- Lynne A. Okada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Slot via filled dual damascene interconnect structure without middl...
- Patent number 6,603,206
- Issue date Aug 5, 2003
- Advanced Micro Devices, Inc.
- Fei Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Plasma etch process for nonhomogenous film
- Patent number 6,599,839
- Issue date Jul 29, 2003
- Advanced Micro Devices, Inc.
- Calvin T. Gabriel
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Post-treatment of low-k dielectric for prevention of photoresist po...
- Patent number 6,583,046
- Issue date Jun 24, 2003
- Advanced Micro Devices, Inc.
- Lynne A. Okada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Pre-treatment of low-k dielectric for prevention of photoresist poi...
- Patent number 6,534,397
- Issue date Mar 18, 2003
- Advanced Micro Devices, Inc.
- Lynne A. Okada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Via filled dual damascene structure with middle stop layer and meth...
- Patent number 6,521,524
- Issue date Feb 18, 2003
- Advanced Micro Devices, Inc.
- Fei Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integration of organic fill for dual damascene process
- Patent number 6,514,860
- Issue date Feb 4, 2003
- Advanced Micro Devices, Inc.
- Lynne A. Okada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Use of hydrogen doping for protection of low-k dielectric layers
- Patent number 6,495,447
- Issue date Dec 17, 2002
- Advanced Micro Devices, Inc.
- Lynne A. Okada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Carrier gas modification for use in plasma ashing of photoresist
- Patent number 6,492,272
- Issue date Dec 10, 2002
- Advanced Micro Devices, Inc.
- Lynne A. Okada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a semiconductor structure with treatment to...
- Patent number 6,475,929
- Issue date Nov 5, 2002
- Advanced Micro Devices, Inc.
- Calvin T. Gabriel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dielectric layer with treated top surface forming an etch stop laye...
- Patent number 6,472,231
- Issue date Oct 29, 2002
- Advanced Micro Devices, Inc.
- Calvin T. Gabriel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Via filled dual damascene structure with middle stop layer and meth...
- Patent number 6,465,340
- Issue date Oct 15, 2002
- Advanced Micro Devices, Inc.
- Fei Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon carbide barc in dual damascene processing
- Patent number 6,465,889
- Issue date Oct 15, 2002
- Advanced Micro Devices, Inc.
- Ramkumar Subramanian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Carrier gas modification for preservation of mask layer during plas...
- Patent number 6,451,673
- Issue date Sep 17, 2002
- Advanced Micro Devices, Inc.
- Lynne A. Okada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ultra thin etch stop layer for damascene process
- Patent number 6,448,654
- Issue date Sep 10, 2002
- Advanced Micro Devices, Inc.
- Calvin T. Gabriel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making a slot via filled dual damascene structure with a...
- Patent number 6,444,573
- Issue date Sep 3, 2002
- Advanced Micro Devices, Inc.
- Fei Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a slot dual damascene structure without middl...
- Patent number 6,429,116
- Issue date Aug 6, 2002
- Advanced Micro Devices, Inc.
- Fei Wang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Air gap dual damascene process and structure
- Publication number 20040232552
- Publication date Nov 25, 2004
- Advanced Micro Devices, Inc.
- Fei Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Slot via filled dual damascene structure without middle stop layer...
- Publication number 20020106889
- Publication date Aug 8, 2002
- Advanced Micro Devices, Inc.
- Fei Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FABRICATING A SLOT DUAL DAMASCENE STRUCTURE WITHOUT MIDDL...
- Publication number 20020106885
- Publication date Aug 8, 2002
- Advanced Micro Devices, Inc.
- Fei Wang
- H01 - BASIC ELECTRIC ELEMENTS

Lynne A. Okada

Person

Patents Grantslast 30 patents

Method for forming inlaid structures for IC interconnections

Ultra low dielectric constant integrated circuit system

Sealing sidewall pores in low-k dielectrics

Interconnect with multiple layers of conductive material with grain...

Method for reworking a multi-layer photoresist following an underla...

N-containing plasma etch process with reduced resist poisoning

Method for forming dual inlaid structures for IC interconnections

Method for forming dual damascene interconnect structure

Vapor treatment for repairing damage of low-k dielectric

Polymer spacers for creating small geometry space and method of man...

Dual damascene metal interconnect structure with dielectric studs

Dual damascene with silicon carbide middle etch stop layer/ARC

Method for forming an interconnect structure using a CVD organic BA...

Plasma etching using combination of CHF3 and CH3F

Slot via filled dual damascene interconnect structure without middl...

Plasma etch process for nonhomogenous film

Post-treatment of low-k dielectric for prevention of photoresist po...

Pre-treatment of low-k dielectric for prevention of photoresist poi...

Via filled dual damascene structure with middle stop layer and meth...

Integration of organic fill for dual damascene process

Use of hydrogen doping for protection of low-k dielectric layers

Carrier gas modification for use in plasma ashing of photoresist

Method of manufacturing a semiconductor structure with treatment to...

Dielectric layer with treated top surface forming an etch stop laye...

Via filled dual damascene structure with middle stop layer and meth...

Silicon carbide barc in dual damascene processing

Carrier gas modification for preservation of mask layer during plas...

Ultra thin etch stop layer for damascene process

Method of making a slot via filled dual damascene structure with a...

Method of fabricating a slot dual damascene structure without middl...

Patents Applicationslast 30 patents

Air gap dual damascene process and structure

Slot via filled dual damascene structure without middle stop layer...

METHOD OF FABRICATING A SLOT DUAL DAMASCENE STRUCTURE WITHOUT MIDDL...