Mahbub M. Rashed

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device with transistor local interconnects
- Patent number 12,148,702
- Issue date Nov 19, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Mahbub Rashed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Post-manufacture latch timing control blocks in pipelined processors
- Patent number 12,050,485
- Issue date Jul 30, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Vivek Raj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor structure including sectioned well region
- Patent number 12,046,603
- Issue date Jul 23, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Navneet Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Back bias control for always-on circuit section enabling leakage re...
- Patent number 11,979,145
- Issue date May 7, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Navneet K. Jain
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Deep nwell contact structures
- Patent number 11,929,399
- Issue date Mar 12, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Navneet K. Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method for delaying of data signal from pulse latch w...
- Patent number 11,894,845
- Issue date Feb 6, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Navneet K. Jain
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit structure and related method for radiation resistant memory...
- Patent number 11,862,240
- Issue date Jan 2, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Vivek Raj
- G11 - INFORMATION STORAGE
Information Patent Grant
Low-leakage sense circuit, memory circuit incorporating the low-lea...
- Patent number 11,495,288
- Issue date Nov 8, 2022
- GLOBALFOUNDRIES U.S. Inc.
- Vivek Raj
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device with transistor local interconnects
- Patent number 11,444,031
- Issue date Sep 13, 2022
- GLOBALFOUNDRIES U.S. INC.
- Mahbub Rashed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Single-rail memory circuit with row-specific voltage supply lines a...
- Patent number 11,322,200
- Issue date May 3, 2022
- GLOBALFOUNDRIES U.S. Inc.
- Vivek Raj
- G11 - INFORMATION STORAGE
Information Patent Grant
Low clock load dynamic dual output latch circuit
- Patent number 11,218,137
- Issue date Jan 4, 2022
- GLOBALFOUNDRIES U.S. Inc.
- Uttam Saha
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic single input-dual output latch
- Patent number 11,050,414
- Issue date Jun 29, 2021
- GLOBALFOUNDRIES U.S. Inc.
- Uttam Saha
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor device with transistor local interconnects
- Patent number 10,833,018
- Issue date Nov 10, 2020
- GLOBALFOUNDRIES Inc.
- Mahbub Rashed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electrostatic discharge protection device
- Patent number 10,819,110
- Issue date Oct 27, 2020
- GLOBALFOUNDRIES Inc.
- Anil Kumar
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Positive and negative full-range back-bias generator circuit structure
- Patent number 10,678,287
- Issue date Jun 9, 2020
- GLOBALFOUNDRIES Inc.
- Arif A. Siddiqi
- G11 - INFORMATION STORAGE
Information Patent Grant
Structure and method for flexible power staple insertion
- Patent number 10,658,294
- Issue date May 19, 2020
- GLOBALFOUNDRIES Inc.
- Juhan Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structure and method for flexible power staple insertion
- Patent number 10,366,954
- Issue date Jul 30, 2019
- GLOBALFOUNDRIES Inc.
- Juhan Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Context aware processing to resolve strong spacing effects due to s...
- Patent number 10,360,334
- Issue date Jul 23, 2019
- GLOBALFOUNDRIES Inc.
- Navneet Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
FDSOI semiconductor device with contact enhancement layer and metho...
- Patent number 10,347,543
- Issue date Jul 9, 2019
- GLOBALFOUNDRIES Inc.
- Peter Baars
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method, apparatus, and system for improved memory cell design havin...
- Patent number 10,340,288
- Issue date Jul 2, 2019
- GLOBALFOUNDRIES Inc.
- Juhan Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Calibration devices for I/O driver circuits having switches biased...
- Patent number 10,333,497
- Issue date Jun 25, 2019
- GLOBALFOUNDRIES Inc.
- Anil Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-chip voltage generator for back-biasing field effect transistors...
- Patent number 10,303,196
- Issue date May 28, 2019
- GLOBALFOUNDRIES Inc.
- Navneet Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit design having aligned power staples
- Patent number 10,242,946
- Issue date Mar 26, 2019
- GLOBALFOUNDRIES Inc.
- Irene Y. L. Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Special construct for continuous non-uniform active region FinFET s...
- Patent number 10,199,378
- Issue date Feb 5, 2019
- GLOBALFOUNDRIES Inc.
- Navneet Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method, apparatus and system for forming recolorable standard cells...
- Patent number 10,108,771
- Issue date Oct 23, 2018
- GLOBALFOUNDRIES Inc.
- Juhan Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Antenna diode circuit for manufacturing of semiconductor devices
- Patent number 10,096,595
- Issue date Oct 9, 2018
- GLOBALFOUNDRIES Inc.
- Juhan Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Special construct for continuous non-uniform active region FinFET s...
- Patent number 9,893,063
- Issue date Feb 13, 2018
- GLOBALFOUNDRIES Inc.
- Navneet Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method, apparatus and system for using hybrid library track design...
- Patent number 9,842,184
- Issue date Dec 12, 2017
- GLOBALFOUNDRIES Inc.
- Anurag Mittal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Special construct for continuous non-uniform RX FinFET standard cells
- Patent number 9,634,003
- Issue date Apr 25, 2017
- GLOBALFOUNDRIES Inc.
- Navneet Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wide pin for improved circuit routing
- Patent number 9,536,035
- Issue date Jan 3, 2017
- GLOBALFOUNDRIES Inc.
- Lei Yuan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR STRUCTURE INCLUDING SECTIONED WELL REGION
- Publication number 20240282776
- Publication date Aug 22, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Navneet Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE WITH MULTI-ROW CELL FOR ACCOMMODATING...
- Publication number 20240222356
- Publication date Jul 4, 2024
- GLOBALFOUNDRIES U.S. Inc.
- James P. Mazza
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD FOR DELAYING OF DATA SIGNAL FROM PULSE LATCH W...
- Publication number 20240072771
- Publication date Feb 29, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Navneet K. Jain
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE WITH CELLS HAVING ASYMMETRIC POWER RAIL
- Publication number 20240021621
- Publication date Jan 18, 2024
- GLOBALFOUNDRIES U.S. Inc.
- James P. Mazza
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CROSS COUPLE DESIGN FOR HIGH DENSITY STANDARD CELLS
- Publication number 20230395675
- Publication date Dec 7, 2023
- GLOBALFOUNDRIES U.S. Inc.
- James P. MAZZA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POST-MANUFACTURE LATCH TIMING CONTROL BLOCKS IN PIPELINED PROCESSORS
- Publication number 20230341888
- Publication date Oct 26, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Vivek Raj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOCAL INTERCONNECT POWER RAILS AND UPPER POWER RAILS
- Publication number 20230335484
- Publication date Oct 19, 2023
- GLOBALFOUNDRIES U.S. Inc.
- James P. MAZZA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CIRCUIT STRUCTURE AND RELATED METHOD FOR RADIATION RESISTANT MEMORY...
- Publication number 20230326520
- Publication date Oct 12, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Vivek Raj
- G11 - INFORMATION STORAGE
Information Patent Application
DEEP NWELL CONTACT STRUCTURES
- Publication number 20230282707
- Publication date Sep 7, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Navneet K. Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CELL LAYOUTS
- Publication number 20230268335
- Publication date Aug 24, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Juhan KIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM AND METHOD EMPLOYING POWER-OPTIMIZED TIMING CLOSURE
- Publication number 20230267259
- Publication date Aug 24, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Navneet Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR STRUCTURE INCLUDING SECTIONED WELL REGION
- Publication number 20230163134
- Publication date May 25, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Navneet Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE WITH TRANSISTOR LOCAL INTERCONNECTS
- Publication number 20220367360
- Publication date Nov 17, 2022
- GLOBALFOUNDRIES U.S. Inc.
- Mahbub Rashed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW-LEAKAGE SENSE CIRCUIT, MEMORY CIRCUIT INCORPORATING THE LOW-LEA...
- Publication number 20220215872
- Publication date Jul 7, 2022
- GLOBALFOUNDRIES U.S. Inc.
- Vivek Raj
- G11 - INFORMATION STORAGE
Information Patent Application
LOW CLOCK LOAD DYNAMIC DUAL OUTPUT LATCH CIRCUIT
- Publication number 20210320650
- Publication date Oct 14, 2021
- GLOBALFOUNDRIES U.S. Inc.
- Uttam SAHA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SEMICONDUCTOR DEVICE WITH TRANSISTOR LOCAL INTERCONNECTS
- Publication number 20210013150
- Publication date Jan 14, 2021
- GLOBALFOUNDRIES INC.
- Mahbub Rashed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POSITIVE AND NEGATIVE FULL-RANGE BACK-BIAS GENERATOR CIRCUIT STRUCTURE
- Publication number 20200117226
- Publication date Apr 16, 2020
- GLOBALFOUNDRIES INC.
- Arif A. Siddiqi
- G05 - CONTROLLING REGULATING
Information Patent Application
STRUCTURE AND METHOD FOR FLEXIBLE POWER STAPLE INSERTION
- Publication number 20190333853
- Publication date Oct 31, 2019
- GLOBALFOUNDRIES INC.
- Juhan Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE WITH TRANSISTOR LOCAL INTERCONNECTS
- Publication number 20190326219
- Publication date Oct 24, 2019
- Mahbub Rashed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTROSTATIC DISCHARGE PROTECTION DEVICE
- Publication number 20190267801
- Publication date Aug 29, 2019
- GLOBALFOUNDRIES INC.
- Anil KUMAR
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
FDSOI SEMICONDUCTOR DEVICE WITH CONTACT ENHANCEMENT LAYER AND METHO...
- Publication number 20190148245
- Publication date May 16, 2019
- GLOBALFOUNDRIES INC.
- Peter Baars
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER RAIL AND MOL CONSTRUCTS FOR FDSOI
- Publication number 20180315708
- Publication date Nov 1, 2018
- GLOBALFOUNDRIES INC.
- Anurag MITTAL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTEXT AWARE PROCESSING TO RESOLVE STRONG SPACING EFFECTS DUE TO S...
- Publication number 20180225406
- Publication date Aug 9, 2018
- GLOBALFOUNDRIES INC.
- Navneet Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT DESIGN HAVING ALIGNED POWER STAPLES
- Publication number 20180218981
- Publication date Aug 2, 2018
- GLOBALFOUNDRIES INC.
- Irene Y. L. Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPECIAL CONSTRUCT FOR CONTINUOUS NON-UNIFORM ACTIVE REGION FINFET S...
- Publication number 20180122804
- Publication date May 3, 2018
- GLOBALFOUNDRIES INC.
- Navneet JAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD, APPARATUS, AND SYSTEM FOR IMPROVED MEMORY CELL DESIGN HAVIN...
- Publication number 20180040631
- Publication date Feb 8, 2018
- GLOBALFOUNDRIES INC.
- Juhan Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD, APPARATUS AND SYSTEM FOR FORMING RECOLORABLE STANDARD CELLS...
- Publication number 20170316140
- Publication date Nov 2, 2017
- GLOBALFOUNDRIES Inc.
- Juhan Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPECIAL CONSTRUCT FOR CONTINUOUS NON-UNIFORM ACTIVE REGION FINFET S...
- Publication number 20170141109
- Publication date May 18, 2017
- GLOBALFOUNDRIES INC.
- Navneet JAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ANTENNA DIODE CIRCUIT FOR MANUFACTURING OF SEMICONDUCTOR DEVICES
- Publication number 20170125403
- Publication date May 4, 2017
- GLOBALFOUNDRIES INC.
- Juhan Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS AND SYSTEM FOR USING HYBRID LIBRARY TRACK DESIGN...
- Publication number 20170076031
- Publication date Mar 16, 2017
- GLOBALFOUNDRIES INC.
- Anurag Mittal
- G06 - COMPUTING CALCULATING COUNTING

Mahbub M. Rashed

Person

Patents Grantslast 30 patents

Semiconductor device with transistor local interconnects

Post-manufacture latch timing control blocks in pipelined processors

Semiconductor structure including sectioned well region

Back bias control for always-on circuit section enabling leakage re...

Deep nwell contact structures

Structure and method for delaying of data signal from pulse latch w...

Circuit structure and related method for radiation resistant memory...

Low-leakage sense circuit, memory circuit incorporating the low-lea...

Semiconductor device with transistor local interconnects

Single-rail memory circuit with row-specific voltage supply lines a...

Low clock load dynamic dual output latch circuit

Dynamic single input-dual output latch

Semiconductor device with transistor local interconnects

Electrostatic discharge protection device

Positive and negative full-range back-bias generator circuit structure

Structure and method for flexible power staple insertion

Structure and method for flexible power staple insertion

Context aware processing to resolve strong spacing effects due to s...

FDSOI semiconductor device with contact enhancement layer and metho...

Method, apparatus, and system for improved memory cell design havin...

Calibration devices for I/O driver circuits having switches biased...

On-chip voltage generator for back-biasing field effect transistors...

Circuit design having aligned power staples

Special construct for continuous non-uniform active region FinFET s...

Method, apparatus and system for forming recolorable standard cells...

Antenna diode circuit for manufacturing of semiconductor devices

Special construct for continuous non-uniform active region FinFET s...

Method, apparatus and system for using hybrid library track design...

Special construct for continuous non-uniform RX FinFET standard cells

Wide pin for improved circuit routing

Patents Applicationslast 30 patents

SEMICONDUCTOR STRUCTURE INCLUDING SECTIONED WELL REGION

INTEGRATED CIRCUIT STRUCTURE WITH MULTI-ROW CELL FOR ACCOMMODATING...

STRUCTURE AND METHOD FOR DELAYING OF DATA SIGNAL FROM PULSE LATCH W...

INTEGRATED CIRCUIT STRUCTURE WITH CELLS HAVING ASYMMETRIC POWER RAIL

CROSS COUPLE DESIGN FOR HIGH DENSITY STANDARD CELLS

POST-MANUFACTURE LATCH TIMING CONTROL BLOCKS IN PIPELINED PROCESSORS

LOCAL INTERCONNECT POWER RAILS AND UPPER POWER RAILS

CIRCUIT STRUCTURE AND RELATED METHOD FOR RADIATION RESISTANT MEMORY...

DEEP NWELL CONTACT STRUCTURES

CELL LAYOUTS

SYSTEM AND METHOD EMPLOYING POWER-OPTIMIZED TIMING CLOSURE

SEMICONDUCTOR STRUCTURE INCLUDING SECTIONED WELL REGION

SEMICONDUCTOR DEVICE WITH TRANSISTOR LOCAL INTERCONNECTS

LOW-LEAKAGE SENSE CIRCUIT, MEMORY CIRCUIT INCORPORATING THE LOW-LEA...

LOW CLOCK LOAD DYNAMIC DUAL OUTPUT LATCH CIRCUIT

SEMICONDUCTOR DEVICE WITH TRANSISTOR LOCAL INTERCONNECTS

POSITIVE AND NEGATIVE FULL-RANGE BACK-BIAS GENERATOR CIRCUIT STRUCTURE

STRUCTURE AND METHOD FOR FLEXIBLE POWER STAPLE INSERTION

SEMICONDUCTOR DEVICE WITH TRANSISTOR LOCAL INTERCONNECTS

ELECTROSTATIC DISCHARGE PROTECTION DEVICE

FDSOI SEMICONDUCTOR DEVICE WITH CONTACT ENHANCEMENT LAYER AND METHO...

POWER RAIL AND MOL CONSTRUCTS FOR FDSOI

CONTEXT AWARE PROCESSING TO RESOLVE STRONG SPACING EFFECTS DUE TO S...

CIRCUIT DESIGN HAVING ALIGNED POWER STAPLES

SPECIAL CONSTRUCT FOR CONTINUOUS NON-UNIFORM ACTIVE REGION FINFET S...

METHOD, APPARATUS, AND SYSTEM FOR IMPROVED MEMORY CELL DESIGN HAVIN...

METHOD, APPARATUS AND SYSTEM FOR FORMING RECOLORABLE STANDARD CELLS...

SPECIAL CONSTRUCT FOR CONTINUOUS NON-UNIFORM ACTIVE REGION FINFET S...

ANTENNA DIODE CIRCUIT FOR MANUFACTURING OF SEMICONDUCTOR DEVICES

METHOD, APPARATUS AND SYSTEM FOR USING HYBRID LIBRARY TRACK DESIGN...