Patent Application
20180315708
The present invention generally relates to the design of interconnect structures for semiconductor devices. More particularly, the present invention relates to a power rail construct and related MOL constructs for gate-first semiconductor device technologies.
CMOS bulk and FinFET technologies are running into design blocks and reliability issues with trench silicide use (e.g., V0 shorting to the trench silicide) as semiconductor devices continue to scale downward, for example, below 14 nm, so the industry is moving toward fully-depleted silicon-on-insulator (FDSOI), a gate-first technology, as a replacement for CMOS bulk and FinFET technologies. The library cells for the design of the interconnect structures for the scaled-down devices likewise have to scale downward. However, fundamental changes to the existing power structure are needed to scale down such interconnect design.
The shortcomings of the prior art are overcome and additional advantages are provided through the provision, in one aspect, of a semiconductor structure. The semiconductor structure comprises at least one source or drain region of at least one semiconductor device, a first metallization layer of an interconnect structure for the at least one semiconductor device, at least one first contact area electrically coupled to the at least one source or drain region, at least one second contact area electrically coupled to the at least one first contact area, at least one V0 electrically coupled to the at least one second contact area, the first metallization layer being electrically coupled to the at least one V0, and at least one first gate and at least one second gate, the at least one first gate and the at least one second gate are metal gates. The at least one source or drain region is situated adjacent one or more of the at least one first gate and the at least one second gate, the at least one second contact area is also electrically coupled to one or more of the at least one first gate and the at least one second gate, trench silicide is absent from the semiconductor structure, and the semiconductor structure is planar.
In accordance with another aspect, a semiconductor structure is provided. The semiconductor structure comprises at least one source or drain region of at least one semiconductor device, at least one first contact area electrically coupled to the at least one source or drain region, at least one second contact area electrically coupled to the at least one first contact area, at least one V0 bi-directional staple adjacent the at least one second contact area and electrically coupled to the at least one second contact area and the at least one first contact area, and at least one V0 above and electrically coupled to the at least one second contact area and the at least one V0 bi-directional staple. The semiconductor structure further comprises at least one first gate and at least one second gate, the at least one first gate and the at least one second gate are metal gates, the at least one source or drain region is situated adjacent one or more of the at least one first gate and the at least one second gate, the at least one second contact area is also electrically coupled to one or more of the at least one first gate and the at least one second gate, trench silicide is absent from the semiconductor structure, and the semiconductor structure is planar.
In accordance with yet another aspect, a semiconductor structure is provided. The semiconductor structure comprises at least one first contact area, at least one second contact area above and electrically coupled to the at least one first contact area, at least one V0 bi-directional staple adjacent the at least one second contact area and electrically coupled to the at least one second contact area and the at least one first contact area, at least one V0 above and electrically coupled to the at least one second contact area and the at least one V0 bi-directional staple, and a first metallization layer power rail electrically coupled to the at least one V0, the first metallization power rail is made of a non-copper heavy metal having a minimum area less than that of copper, and the at least one first contact area, the at least one second contact area, the at least one V0 bi-directional staple and the at least one V0, together serve as a power rail spine.
These, and other objects, features and advantages of this invention will become apparent from the following detailed description of the various aspects of the invention taken in conjunction with the accompanying drawings, in which:
Aspects of the present invention and certain features, advantages, and details thereof, are explained more fully below with reference to the non-limiting examples illustrated in the accompanying drawings. Descriptions of well-known materials, fabrication tools, processing techniques, etc., are omitted so as not to unnecessarily obscure the invention in detail. It should be understood, however, that the detailed description and the specific examples, while indicating aspects of the invention, are given by way of illustration only, and are not by way of limitation. Various substitutions, modifications, additions, and/or arrangements, within the spirit and/or scope of the underlying inventive concepts will be apparent to those skilled in the art from this disclosure.
Approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “about,” is not limited to the precise value specified. In some instances, the approximating language may correspond to the precision of an instrument for measuring the value.
The terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise” (and any form of comprise, such as “comprises” and “comprising”), “have” (and any form of have, such as “has” and “having”), “include (and any form of include, such as “includes” and “including”), and “contain” (and any form of contain, such as “contains” and “containing”) are open-ended linking verbs. As a result, a method or device that “comprises,” “has,” “includes” or “contains” one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements. Likewise, a step of a method or an element of a device that “comprises,” “has,” “includes” or “contains” one or more features possesses those one or more features, but is not limited to possessing only those one or more features. Furthermore, a device or structure that is configured in a certain way is configured in at least that way, but may also be configured in ways that are not listed.
As used herein, the term “connected,” when used to refer to two physical elements, means a direct connection between the two physical elements. The term “coupled,” however, can mean a direct connection or a connection through one or more intermediary elements.
As used herein, the terms “may” and “may be” indicate a possibility of an occurrence within a set of circumstances; a possession of a specified property, characteristic or function; and/or qualify another verb by expressing one or more of an ability, capability, or possibility associated with the qualified verb. Accordingly, usage of “may” and “may be” indicates that a modified term is apparently appropriate, capable, or suitable for an indicated capacity, function, or usage, while taking into account that in some circumstances the modified term may sometimes not be appropriate, capable or suitable. For example, in some circumstances, an event or capacity can be expected, while in other circumstances the event or capacity cannot occur—this distinction is captured by the terms “may” and “may be.”
As used herein, unless otherwise specified, the term “about” used with a value, such as measurement, size, etc., means a possible variation of plus or minus five percent of the value. Also, where used, the term “low-k dielectric” refers to a dielectric with a dielectric constant k<3.9.
As used herein, “about” or “approximately” indicate +/−5% of the value(s) stated.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” or “over” the other elements or features. Thus, the exemplary term “below” may encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly. When the phrase “at least one of” is applied to a list, it is being applied to the entire list, and not to the individual members of the list.
Reference is made below to the drawings, which may not be drawn to scale for ease of understanding, wherein the same reference numbers may be used throughout different figures to designate the same or similar components.
The present invention moves semiconductor device interconnect power design forward by providing a power rail construct that includes V0, (i.e., a via-filled contact to a first metallization layer of an interconnect structure), and breaks the contact area (CA) into a first contact area and a second contact area for middle-of-the-line (MOL) gate-first technology (e.g., FDSOI devices). Preferably, the power rails and contact areas are made of a non-copper heavy metal having a minimum area less than that of copper (e.g., tungsten and/or cobalt) providing a thinner power rail, and no barrier material is needed for smaller geometries, such a power rail construct being useful for semiconductor devices, such as, for example, logic, memory and analog applications. Placement of V0 along a center line of the non-copper power rail enables shrinking the standard cell library below 7.5 tracks. A V0 staple in the power rail spine replaces a conventional zig-zag design. Also provided is to combine the second contact area with CB (gate contact) to save an additional mask. Further provided is a CA-based power rail spine.
As shown in
The semiconductor structure of
In one example, substrate 102 may include any silicon-containing substrate including, but not limited to, silicon (Si), single crystal silicon, polycrystalline Si, amorphous Si, silicon-on-nothing (SON), silicon-on-insulator (SOI) or silicon-on-replacement insulator (SRI) or silicon germanium substrates and the like. Substrate 102 may in addition or instead include various isolations, dopings and/or device features. The substrate may include other suitable elementary semiconductors, such as, for example, germanium (Ge) in crystal, a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb) or combinations thereof; an alloy semiconductor including GaAsP, AlInAs, GaInAs, GaInP, or GaInAsP or combinations thereof.
In one example, via-type connection 214 of
The construct of
Using a CA-based spine allows for a reduction in width of a first metallization layer (M1) power rail (see
As compared to conventional V0 placement, centering V0 together with a thinner non-copper power rail allows for the reduction in the number of tracks. The thinner power rail is enabled by the CA1-based spine that includes the stitch of
In a first aspect, disclosed above is a semiconductor structure. The semiconductor structure includes source or drain region(s) of semiconductor device(s), a first metallization layer of an interconnect structure for the semiconductor device(s), first contact area(s) electrically coupled to the source or drain region(s), second contact area(s) electrically coupled to the first contact area(s), and V0(s) electrically coupled to the second contact area(s), the first metallization layer being electrically coupled to the V0(s). The semiconductor structure further includes first gate(s) and second gate(s), the first gate(s) and the second gate(s) are metal gates, the source or drain region(s) is situated adjacent one or more of the first gate(s) and the second gate(s), and the second contact area(s) is also electrically coupled to one or more of the first gate(s) and the second gate(s). Trench silicide is absent from the semiconductor structure, and the semiconductor structure is planar.
In one example, the first contact area(s) and the second contact area(s) are made of a non-copper heavy metal having a minimum area less than that of copper. In one example, the non-copper heavy metal may include, for example, tungsten and/or cobalt.
In a second aspect, disclosed above is a semiconductor structure. The semiconductor structure includes source or drain region(s) of semiconductor device(s), first contact area(s) electrically coupled to the source or drain region(s), second contact area(s) electrically coupled to the first contact area(s), V0 bi directional staple(s) adjacent the second contact area(s) and electrically coupled to the second contact area(s) and the first contact area(s), V0(s) above and electrically coupled to the second contact area(s) and the V0 bi-directional staple(s). The semiconductor structure further includes first gate(s) and second gate(s), the first gate(s) and the second gate(s) are metal gates, the source or drain region(s) is situated adjacent one or more of the first gate(s) and the second gate(s), and the second contact area(s) is also electrically coupled to one or more of the first gate(s) and the second gate(s). Trench silicide is absent from the semiconductor structure, and the semiconductor structure is planar.
In one example, the source or drain region(s) may include, for example, epitaxial semiconductor material.
In one example, the semiconductor structure of the second aspect may further include, for example, a via-type gate contact electrically coupling the second contact area(s) and the one or more of the first gate(s) and the second gate(s). In one example, the semiconductor structure may further include, for example, a jumper from the second contact area(s) to the one or more of the first gate(s) and the second gate(s).
In one example, the semiconductor structure of the second aspect may further include, for example, a local interconnect, one or more of the V0(s) being electrically coupled to the local interconnect.
In one example, the semiconductor structure of the second aspect may further include, for example, a first metallization layer power rail, and one or more of the V0(s) is electrically coupled to the first metallization layer power rail. In one example, the first metallization layer power rail may be, for example, made of non-copper heavy metal having a minimum area less than that of copper. In one example, the non-copper heavy metal is made of tungsten and/or cobalt.
In one example, the V0(s) may be, for example, situated along a center length of the first metallization layer power rail. In one example, the V0(s) may include, for example, at least two V0, the at least two V0 being randomly electrically coupled to the first metallization layer power rail along a center length thereof.
In one example, the first contact area(s) and the second contact area(s) may be, for example, made of a non-copper heavy metal having a minimum area less than that of copper. In one example, the non-copper heavy metal may include, for example, tungsten and/or cobalt.
In a third aspect, disclosed above is a semiconductor structure. The semiconductor structure includes first contact area(s), second contact area(s) above and electrically coupled to the first contact area(s), V0 bi-directional staple(s) adjacent the second contact area(s) and electrically coupled to the second contact area(s) and the first contact area(s). The semiconductor structure further includes V0(s) above and electrically coupled to the second contact area(s) and the V0 bi-directional staple(s), and a first metallization layer power rail electrically coupled to the V0(s), the first metallization power rail being made of a non-copper heavy metal having a minimum area less than that of copper. The first contact area(s), the second contact area(s), the V0 bi-directional staple(s) and the V0(s), together with the first metallization layer power rail serve as a power rail spine.
In one example, the non-copper heavy metal may include, for example, tungsten and/or cobalt.
In one example, the V0(s) of the semiconductor structure of the third aspect may be, for example, situated along a center length of the first metallization layer power rail.
In one example, the first contact area(s) and the second contact area(s) may be, for example, made of a non-copper heavy metal having a minimum area less than that of copper. In one example, the non-copper heavy metal may include, for example, tungsten and/or cobalt.
While several aspects of the present invention have been described and depicted herein, alternative aspects may be effected by those skilled in the art to accomplish the same objectives. Accordingly, it is intended by the appended claims to cover all such alternative aspects as fall within the true spirit and scope of the invention.
