MALAY GANAI

Person

PLAINSBORO, NJ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Scenario driven concurrency bugs: model and check
- Patent number 8,707,272
- Issue date Apr 22, 2014
- NEC Laboratories America, Inc.
- Malay Ganai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for model checking by interleaving stateless and...
- Patent number 8,589,126
- Issue date Nov 19, 2013
- NEC Laboratories America, Inc.
- Malay K. Ganai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for model checking the precision of programs em...
- Patent number 8,539,451
- Issue date Sep 17, 2013
- NEC Laboratories America, Inc.
- Franjo Ivancic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient decision method for real non-linear arithmetic constraints
- Patent number 8,539,013
- Issue date Sep 17, 2013
- NEC Laboratories America, Inc.
- Malay K. Ganai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrating interval constraint propagation with nonlinear real ari...
- Patent number 8,538,900
- Issue date Sep 17, 2013
- NEC Laboratories America, Inc.
- Malay K. Ganai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DPLL-based SAT solver using with application-aware branching
- Patent number 8,532,971
- Issue date Sep 10, 2013
- NEC Laboratories America, Inc.
- Malay K. Ganai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallelizing bounded model checking using tunnels over a distribut...
- Patent number 8,504,330
- Issue date Aug 6, 2013
- NEC Laboratories America, Inc.
- Malay Ganai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for reducing verification conditions for concur...
- Patent number 8,448,145
- Issue date May 21, 2013
- NEC Laboratories America, Inc.
- Malay K. Ganai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Software verification using range analysis
- Patent number 8,131,532
- Issue date Mar 6, 2012
- NEC Laboratories America, Inc.
- Srihari Cadambi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient decision procedure for bounded integer non-linear operati...
- Patent number 8,131,661
- Issue date Mar 6, 2012
- NEC Laboratories America, Inc.
- Malay K. Ganai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modeling and verification of concurrent systems using SMT-based BMC
- Patent number 8,005,661
- Issue date Aug 23, 2011
- NEC Laboratories America, Inc.
- Malay Ganai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for tunneling and slicing based BMC decomposition
- Patent number 7,949,511
- Issue date May 24, 2011
- NEC Laboratories America, Inc.
- Malay K. Ganai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Software verification
- Patent number 7,930,659
- Issue date Apr 19, 2011
- NEC Laboratories America, Inc.
- Franjo Ivancic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accelerating high-level bounded model checking
- Patent number 7,853,906
- Issue date Dec 14, 2010
- NEC Laboratories America, Inc.
- Malay Ganai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer implemented method of high-level synthesis for the efficie...
- Patent number 7,743,352
- Issue date Jun 22, 2010
- NEC Laboratories America, Inc.
- Malay Ganai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Iterative abstraction using SAT-based BMC with proof analysis
- Patent number 7,742,907
- Issue date Jun 22, 2010
- NEC Laboratories America, Inc.
- Aarti Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient approaches for bounded model checking
- Patent number 7,711,525
- Issue date May 4, 2010
- NEC Corporation
- Malay Ganai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient modeling of embedded memories in bounded memory checking
- Patent number 7,386,818
- Issue date Jun 10, 2008
- NEC Laboratories America, Inc.
- Malay Ganai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for modeling, abstraction, and analysis of software
- Patent number 7,346,486
- Issue date Mar 18, 2008
- NEC Laboratories America, Inc.
- Franjo Ivancic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient SAT-based unbounded symbolic model checking
- Patent number 7,305,637
- Issue date Dec 4, 2007
- NEC Laboratories America, Inc.
- Malay K. Ganai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient distributed SAT and SAT-based distributed bounded model c...
- Patent number 7,203,917
- Issue date Apr 10, 2007
- NEC Laboratories America, Inc.
- Malay Ganai
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Setsudo: Pertubation-based Testing Framework for Scalable Distribut...
- Publication number 20150081243
- Publication date Mar 19, 2015
- NEC Laboratories America, Inc.
- Malay Ganai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dynamic Taint Analysis of Multi-Threaded Programs
- Publication number 20140108867
- Publication date Apr 17, 2014
- NEC Laboratories America, Inc.
- Malay Ganai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC LIVELOCK ANALYSIS OF MULTI-THREADED PROGRAMS
- Publication number 20130332910
- Publication date Dec 12, 2013
- NEC Laboratories America, Inc.
- Malay K. Ganai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Efficient Checking of Pairwise Reachability in Multi-Threaded Programs
- Publication number 20130205303
- Publication date Aug 8, 2013
- NEC Laboratories America, Inc.
- MALAY GANAI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCENARIO DRIVEN CONCURRENCY BUGS : MODEL AND CHECK
- Publication number 20120174074
- Publication date Jul 5, 2012
- NEC Laboratories America, Inc.
- Malay GANAI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MAT-REDUCED SYMBOLIC ANALYSIS
- Publication number 20120151271
- Publication date Jun 14, 2012
- NEC Laboratories America, Inc.
- Malay GANAI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERVAL ANALYSIS OF CONCURRENT TRACE PROGRAMS USING TRANSACTION SE...
- Publication number 20110246970
- Publication date Oct 6, 2011
- NEC Laboratories America, Inc.
- Malay GANAI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DPLL-BASED SAT SOLVER USING WITH APPLICATION-AWARE BRANCHING
- Publication number 20110184705
- Publication date Jul 28, 2011
- NEC Laboratories America, Inc.
- Malay K. Ganai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATING INTERVAL CONSTRAINT PROPAGATION WITH NONLINEAR REAL AR...
- Publication number 20110173148
- Publication date Jul 14, 2011
- NEC Laboratories America, Inc.
- MALAY K. GANAI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR MODEL CHECKING BY INTERLEAVING STATELESS AND...
- Publication number 20100305919
- Publication date Dec 2, 2010
- NEC Laboratories America, Inc.
- MALAY K. GANAI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR MODEL CHECKING THE PRECISION OF PROGRAMS EM...
- Publication number 20100293530
- Publication date Nov 18, 2010
- NEC Laboratories America, Inc.
- FRANJO IVANCIC
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT DECISION METHOD FOR REAL NON-LINEAR ARITHMETIC CONSTRAINTS
- Publication number 20100281086
- Publication date Nov 4, 2010
- NEC Laboratories America, Inc.
- MALAY K. GANAI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYMBOLIC PREDICTIVE ANALYSIS FOR CONCURRENT PROGRAMS
- Publication number 20100281469
- Publication date Nov 4, 2010
- NEC Laboratories America, Inc.
- Chao Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPLETENESS DETERMINATION IN SMT-BASED BMC FOR SOFTWARE PROGRAMS
- Publication number 20100251222
- Publication date Sep 30, 2010
- NEC LABORATORIES AMERICA
- Malay Ganai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS FOR REDUCING VERIFICATION CONDITIONS FOR CONCUR...
- Publication number 20100088680
- Publication date Apr 8, 2010
- NEC Laboratories America, Inc.
- Malay K. Ganai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLELIZING BOUNDED MODEL CHECKING USING TUNNELS OVER A DISTRIBUT...
- Publication number 20100011057
- Publication date Jan 14, 2010
- NEC Laboratories America, Inc.
- MALAY GANAI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROOF-GUIDED ERROR DIAGNOSIS (PED) BY TRIANGULATION OF PROGRAM ERRO...
- Publication number 20090292941
- Publication date Nov 26, 2009
- NEC Laboratories America, Inc.
- Malay K. Ganai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT DECISION PROCEDURE FOR BOUNDED INTEGER NON-LINEAR OPERATI...
- Publication number 20090222393
- Publication date Sep 3, 2009
- NEC Laboratories America, Inc.
- Malay K. Ganai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARTIAL ORDER REDUCTION FOR SCALABLE TESTING IN SYSTEM LEVEL DESIGN
- Publication number 20090132991
- Publication date May 21, 2009
- NEC Laboratories America, Inc.
- Malay K. Ganai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR TUNNELING AND SLICING BASED BMC DECOMPOSITION
- Publication number 20090125294
- Publication date May 14, 2009
- NEC Laboratories America, Inc.
- Malay K. Ganai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MODELING AND VERIFICATION OF CONCURRENT SYSTEMS USING SMT-BASED BMC
- Publication number 20080281563
- Publication date Nov 13, 2008
- NEC LABORATORIES AMERICA
- Malay GANAI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH-LEVEL SYNTHESIS FOR EFFICIENT VERIFICATION
- Publication number 20070226666
- Publication date Sep 27, 2007
- NEC LABORATORIES AMERICA
- Malay GANAI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCELERATING HIGH-LEVEL BOUNDED MODEL CHECKING
- Publication number 20070226665
- Publication date Sep 27, 2007
- NEC LABORATORIES AMERICA
- Malay GANAI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SOFTWARE VERIFICATION
- Publication number 20060282807
- Publication date Dec 14, 2006
- NEC Laboratories America, Inc.
- Franjo IVANCIC
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Efficient modeling of embedded memories in bounded memory checking
- Publication number 20060190864
- Publication date Aug 24, 2006
- NEC Laboratories America, Inc.
- Malay K. Ganai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Efficient SAT-based unbounded symbolic model checking
- Publication number 20050240885
- Publication date Oct 27, 2005
- NEC Laboratories America, Inc.
- Malay K. Ganai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and method for modeling, abstraction, and analysis of software
- Publication number 20050166167
- Publication date Jul 28, 2005
- NEC Laboratories America, Inc.
- Franjo Ivancic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Iterative abstraction using SAT-based BMC with proof analysis
- Publication number 20040230407
- Publication date Nov 18, 2004
- NEC LABORATORIES AMERICA, INC
- Aarti Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Efficient distributed SAT and SAT-based distributed bounded model c...
- Publication number 20040210860
- Publication date Oct 21, 2004
- NEC LABORATORIES AMERICA, INC
- Malay Ganai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Efficient approaches for bounded model checking
- Publication number 20030225552
- Publication date Dec 4, 2003
- NEC Corporation
- Malay Ganai
- G06 - COMPUTING CALCULATING COUNTING

MALAY GANAI

Person

Patents Grantslast 30 patents

Scenario driven concurrency bugs: model and check

System and method for model checking by interleaving stateless and...

Systems and methods for model checking the precision of programs em...

Efficient decision method for real non-linear arithmetic constraints

Integrating interval constraint propagation with nonlinear real ari...

DPLL-based SAT solver using with application-aware branching

Parallelizing bounded model checking using tunnels over a distribut...

Methods and systems for reducing verification conditions for concur...

Software verification using range analysis

Efficient decision procedure for bounded integer non-linear operati...

Modeling and verification of concurrent systems using SMT-based BMC

System and method for tunneling and slicing based BMC decomposition

Software verification

Accelerating high-level bounded model checking

Computer implemented method of high-level synthesis for the efficie...

Iterative abstraction using SAT-based BMC with proof analysis

Efficient approaches for bounded model checking

Efficient modeling of embedded memories in bounded memory checking

System and method for modeling, abstraction, and analysis of software

Efficient SAT-based unbounded symbolic model checking

Efficient distributed SAT and SAT-based distributed bounded model c...

Patents Applicationslast 30 patents

Setsudo: Pertubation-based Testing Framework for Scalable Distribut...

Dynamic Taint Analysis of Multi-Threaded Programs

DYNAMIC LIVELOCK ANALYSIS OF MULTI-THREADED PROGRAMS

Efficient Checking of Pairwise Reachability in Multi-Threaded Programs

SCENARIO DRIVEN CONCURRENCY BUGS : MODEL AND CHECK

MAT-REDUCED SYMBOLIC ANALYSIS

INTERVAL ANALYSIS OF CONCURRENT TRACE PROGRAMS USING TRANSACTION SE...

DPLL-BASED SAT SOLVER USING WITH APPLICATION-AWARE BRANCHING

INTEGRATING INTERVAL CONSTRAINT PROPAGATION WITH NONLINEAR REAL AR...

SYSTEM AND METHOD FOR MODEL CHECKING BY INTERLEAVING STATELESS AND...

SYSTEMS AND METHODS FOR MODEL CHECKING THE PRECISION OF PROGRAMS EM...

EFFICIENT DECISION METHOD FOR REAL NON-LINEAR ARITHMETIC CONSTRAINTS

SYMBOLIC PREDICTIVE ANALYSIS FOR CONCURRENT PROGRAMS

COMPLETENESS DETERMINATION IN SMT-BASED BMC FOR SOFTWARE PROGRAMS

METHODS AND SYSTEMS FOR REDUCING VERIFICATION CONDITIONS FOR CONCUR...

PARALLELIZING BOUNDED MODEL CHECKING USING TUNNELS OVER A DISTRIBUT...

PROOF-GUIDED ERROR DIAGNOSIS (PED) BY TRIANGULATION OF PROGRAM ERRO...

EFFICIENT DECISION PROCEDURE FOR BOUNDED INTEGER NON-LINEAR OPERATI...

PARTIAL ORDER REDUCTION FOR SCALABLE TESTING IN SYSTEM LEVEL DESIGN

SYSTEM AND METHOD FOR TUNNELING AND SLICING BASED BMC DECOMPOSITION

MODELING AND VERIFICATION OF CONCURRENT SYSTEMS USING SMT-BASED BMC

HIGH-LEVEL SYNTHESIS FOR EFFICIENT VERIFICATION

ACCELERATING HIGH-LEVEL BOUNDED MODEL CHECKING

SOFTWARE VERIFICATION

Efficient modeling of embedded memories in bounded memory checking

Efficient SAT-based unbounded symbolic model checking

System and method for modeling, abstraction, and analysis of software

Iterative abstraction using SAT-based BMC with proof analysis

Efficient distributed SAT and SAT-based distributed bounded model c...

Efficient approaches for bounded model checking