Manoj K. Jain

Person

Plano, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor structure and method for wafer scale chip package
- Patent number 12,125,811
- Issue date Oct 22, 2024
- Texas Instruments Incorporated
- Indumini W. Ranmuthu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-layer polysilicon stack for semiconductor devices
- Patent number 12,080,755
- Issue date Sep 3, 2024
- Texas Instruments Incorporated
- Furen Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reduced ESR in trench capacitor
- Patent number 11,888,021
- Issue date Jan 30, 2024
- Texas Instruments Incorporated
- Jing Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fet construction with copper pillars or bump directly over the fet
- Patent number 11,456,267
- Issue date Sep 27, 2022
- Texas Instruments Incorporated
- Manoj Kumar Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Trench capacitor with warpage reduction
- Patent number 11,271,072
- Issue date Mar 8, 2022
- Texas Instruments Incorporated
- Jiao Jia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of using a sacrificial conductive stack to prevent corrosion
- Patent number 10,811,312
- Issue date Oct 20, 2020
- Texas Instruments Incorporated
- Manoj K. Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated trench capacitor formed in an epitaxial layer
- Patent number 10,720,490
- Issue date Jul 21, 2020
- Texas Instruments Incorporated
- He Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated trench capacitor formed in an epitaxial layer
- Patent number 10,586,844
- Issue date Mar 10, 2020
- Texas Instruments Incorporated
- He Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Trench capacitor with warpage reduction
- Patent number 10,559,650
- Issue date Feb 11, 2020
- Texas Instruments Incorporated
- Jiao Jia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of using a sacrificial conductive stack to prevent corrosion
- Patent number 10,490,448
- Issue date Nov 26, 2019
- Texas Instruments Incorporated
- Manoj K. Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned under bump metal
- Patent number 9,865,555
- Issue date Jan 9, 2018
- Texas Instruments Incorporated
- Manoj K. Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned under bump metal
- Patent number 9,627,334
- Issue date Apr 18, 2017
- Texas Instruments Incorporated
- Manoj K. Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Probe pad design to reduce saw defects
- Patent number 9,607,926
- Issue date Mar 28, 2017
- Texas Instruments Incorporated
- Manoj Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned under bump metal
- Patent number 9,478,510
- Issue date Oct 25, 2016
- Texas Instruments Incorporated
- Manoj K. Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Adhesion of ferroelectric material to underlying conductive capacit...
- Patent number 9,305,998
- Issue date Apr 5, 2016
- Texas Instruments Incorporated
- Bhaskar Srinivasan
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Hydrogen barrier for ferroelectric capacitors
- Patent number 8,778,700
- Issue date Jul 15, 2014
- Texas Instruments Incorporated
- Kezhakkedath R. Udayakumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hydrogen barrier for ferroelectric capacitors
- Patent number 8,779,485
- Issue date Jul 15, 2014
- Texas Instruments Incorporated
- Kezhakkedath R. Udayakumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Electroplated posts with reduced topography and stress
- Patent number 8,476,760
- Issue date Jul 2, 2013
- Texas Instruments Incorporated
- Manoj K. Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hydrogen barrier for ferroelectric capacitors
- Patent number 8,440,508
- Issue date May 14, 2013
- Texas Instruments Incorporated
- Kezhakkedath R. Udayakumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enhancement in throughput and planarity during CMP using a dielectr...
- Patent number 6,653,717
- Issue date Nov 25, 2003
- Texas Instruments Incorporated
- Manoj Kumar Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reflow method for construction of conductive vias
- Patent number 6,627,541
- Issue date Sep 30, 2003
- Texas Instruments Incorporated
- Manoj K. Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Conductor reticulation for improved device planarity
- Patent number 6,495,907
- Issue date Dec 17, 2002
- Texas Instruments Incorporated
- Manoj Kumar Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit interconnect and method
- Patent number 6,358,849
- Issue date Mar 19, 2002
- Texas Instruments Incorporated
- Robert H. Havemann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit insulator and structure using low dielectric ins...
- Patent number 6,278,174
- Issue date Aug 21, 2001
- Texas Instruments Incorporated
- Robert H. Havemann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for removing sub-micro particles from a wafer surface using...
- Patent number 5,711,818
- Issue date Jan 27, 1998
- Texas Instruments Incorporated
- Manoj Kumar Jain
- B08 - CLEANING
Information Patent Grant
Conductor reticulation for improved device planarity
- Patent number 5,686,356
- Issue date Nov 11, 1997
- Texas Instruments Incorporated
- Manoj Kumar Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enhancement in throughput and planarity during CMP using a dielectr...
- Patent number 5,621,241
- Issue date Apr 15, 1997
- Texas Instruments Incorporated
- Manoj K. Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Damascene conductors with embedded pillars
- Patent number 5,602,423
- Issue date Feb 11, 1997
- Texas Instruments Incorporated
- Manoj K. Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Mechanical scrubbing for particle removal
- Patent number 5,551,986
- Issue date Sep 3, 1996
- Taxas Instruments Incorporated
- Manoj K. Jain
- B08 - CLEANING
Information Patent Grant
Enhancement in throughput and planarity during CMP using a dielectr...
- Patent number 5,494,854
- Issue date Feb 27, 1996
- Texas Instruments Incorporated
- Manoj K. Jain
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
MULTI-LAYER POLYSILICON STACK FOR SEMICONDUCTOR DEVICES
- Publication number 20240395854
- Publication date Nov 28, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Furen Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-LOOP TIME VARYING BOSCH PROCESS FOR 2-DIMENSIONAL SMALL CD HI...
- Publication number 20240258112
- Publication date Aug 1, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Chao Zuo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCED ESR IN TRENCH CAPACITOR
- Publication number 20240120368
- Publication date Apr 11, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Jing Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-LAYER POLYSILICON STACK FOR SEMICONDUCTOR DEVICES
- Publication number 20220416014
- Publication date Dec 29, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Furen Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCED ESR IN TRENCH CAPACITOR
- Publication number 20220406885
- Publication date Dec 22, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Jing Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FET CONSTRUCTION WITH COPPER PILLARS OR BUMP DIRECTLY OVER THE FET
- Publication number 20220189898
- Publication date Jun 16, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Manoj Kumar Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IC DEVICE WITH CHIP TO PACKAGE INTERCONNECTS FROM A COPPER METAL IN...
- Publication number 20210375816
- Publication date Dec 2, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Manoj Kumar Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRENCH CAPACITOR WITH WARPAGE REDUCTION
- Publication number 20200161415
- Publication date May 21, 2020
- TEXAS INSTRUMENTS INCORPORATED
- JIAO JIA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED TRENCH CAPACITOR FORMED IN AN EPITAXIAL LAYER
- Publication number 20200152729
- Publication date May 14, 2020
- TEXAS INSTRUMENTS INCORPORATED
- HE LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF USING A SACRIFICIAL CONDUCTIVE STACK TO PREVENT CORROSION
- Publication number 20200058547
- Publication date Feb 20, 2020
- TEXAS INSTRUMENTS INCORPORATED
- Manoj K. JAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE AND METHOD FOR WAFER SCALE CHIP PACKAGE
- Publication number 20190385962
- Publication date Dec 19, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Indumini W. Ranmuthu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRENCH CAPACITOR WITH WARPAGE REDUCTION
- Publication number 20190229181
- Publication date Jul 25, 2019
- TEXAS INSTRUMENTS INCORPORATED
- JIAO JIA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED TRENCH CAPACITOR FORMED IN AN EPITAXIAL LAYER
- Publication number 20190229180
- Publication date Jul 25, 2019
- TEXAS INSTRUMENTS INCORPORATED
- HE LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF USING A SACRIFICIAL CONDUCTIVE STACK TO PREVENT CORROSION
- Publication number 20190206730
- Publication date Jul 4, 2019
- TEXAS INSTRUMENTS INCORPORATED
- Manoj K. JAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED UNDER BUMP METAL
- Publication number 20170179053
- Publication date Jun 22, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Manoj K. JAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED UNDER BUMP METAL
- Publication number 20170018516
- Publication date Jan 19, 2017
- TEXAS INSTRUMENTS INCORPORATED
- Manoj K. JAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED UNDER BUMP METAL
- Publication number 20150179592
- Publication date Jun 25, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Manoj K. JAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROBE PAD DESIGN TO REDUCE SAW DEFECTS
- Publication number 20150170983
- Publication date Jun 18, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Manoj JAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Adhesion of Ferroelectric Material to Underlying Conductive Capacit...
- Publication number 20140227805
- Publication date Aug 14, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Bhaskar Srinivasan
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
HYDROGEN BARRIER FOR FERROELECTRIC CAPACITORS
- Publication number 20130164933
- Publication date Jun 27, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Kezhakkedath R. Udayakumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYDROGEN BARRIER FOR FERROELECTRIC CAPACITORS
- Publication number 20120228739
- Publication date Sep 13, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Kezhakkedath R. Udayakumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ELECTROPLATED POSTS WITH REDUCED TOPOGRAPHY AND STRESS
- Publication number 20120112343
- Publication date May 10, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Manoj K. Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYDROGEN BARRIER FOR FERROELECTRIC CAPACITORS
- Publication number 20110062550
- Publication date Mar 17, 2011
- TEXAS INSTRUMENTS INCORPORATED
- Kezhakkedath R. Udayakumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW COST PROCESS FLOW FOR FABRICATION OF METAL CAPPING LAYER OVER C...
- Publication number 20100155949
- Publication date Jun 24, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Manoj K. Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR PREPARING A METAL FEATURE SURFACE
- Publication number 20080153282
- Publication date Jun 26, 2008
- Texas Instruments, Incorporated
- Manoj K. Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for reducing integrated circuit defects
- Publication number 20050239289
- Publication date Oct 27, 2005
- Nilesh S. Doke
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for reducing integrated circuit defects
- Publication number 20040266185
- Publication date Dec 30, 2004
- TEXAS INSTRUMENTS INCORPORATED
- Nilesh S. Doke
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ENHANCEMENT IN THROUGHPUT AND PLANARITY DURING CMP USING A DIELECTR...
- Publication number 20030075793
- Publication date Apr 24, 2003
- Manoj Kumar Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Prevention of contact failure by hydrogen treatment
- Publication number 20020106881
- Publication date Aug 8, 2002
- Manoj K. Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIELECTRIC STRUCTURE AND METHOD FOR MINIMIZING EROSION DURING CHEMI...
- Publication number 20020055250
- Publication date May 9, 2002
- MANOJ K JAIN
- H01 - BASIC ELECTRIC ELEMENTS

Manoj K. Jain

Person

Patents Grantslast 30 patents

Semiconductor structure and method for wafer scale chip package

Multi-layer polysilicon stack for semiconductor devices

Reduced ESR in trench capacitor

Fet construction with copper pillars or bump directly over the fet

Trench capacitor with warpage reduction

Method of using a sacrificial conductive stack to prevent corrosion

Integrated trench capacitor formed in an epitaxial layer

Integrated trench capacitor formed in an epitaxial layer

Trench capacitor with warpage reduction

Method of using a sacrificial conductive stack to prevent corrosion

Self-aligned under bump metal

Self-aligned under bump metal

Probe pad design to reduce saw defects

Self-aligned under bump metal

Adhesion of ferroelectric material to underlying conductive capacit...

Hydrogen barrier for ferroelectric capacitors

Hydrogen barrier for ferroelectric capacitors

Electroplated posts with reduced topography and stress

Hydrogen barrier for ferroelectric capacitors

Enhancement in throughput and planarity during CMP using a dielectr...

Reflow method for construction of conductive vias

Conductor reticulation for improved device planarity

Integrated circuit interconnect and method

Integrated circuit insulator and structure using low dielectric ins...

Method for removing sub-micro particles from a wafer surface using...

Conductor reticulation for improved device planarity

Enhancement in throughput and planarity during CMP using a dielectr...

Damascene conductors with embedded pillars

Mechanical scrubbing for particle removal

Enhancement in throughput and planarity during CMP using a dielectr...

Patents Applicationslast 30 patents

MULTI-LAYER POLYSILICON STACK FOR SEMICONDUCTOR DEVICES

MULTI-LOOP TIME VARYING BOSCH PROCESS FOR 2-DIMENSIONAL SMALL CD HI...

REDUCED ESR IN TRENCH CAPACITOR

MULTI-LAYER POLYSILICON STACK FOR SEMICONDUCTOR DEVICES

REDUCED ESR IN TRENCH CAPACITOR

FET CONSTRUCTION WITH COPPER PILLARS OR BUMP DIRECTLY OVER THE FET

IC DEVICE WITH CHIP TO PACKAGE INTERCONNECTS FROM A COPPER METAL IN...

TRENCH CAPACITOR WITH WARPAGE REDUCTION

INTEGRATED TRENCH CAPACITOR FORMED IN AN EPITAXIAL LAYER

METHOD OF USING A SACRIFICIAL CONDUCTIVE STACK TO PREVENT CORROSION

SEMICONDUCTOR STRUCTURE AND METHOD FOR WAFER SCALE CHIP PACKAGE

TRENCH CAPACITOR WITH WARPAGE REDUCTION

INTEGRATED TRENCH CAPACITOR FORMED IN AN EPITAXIAL LAYER

METHOD OF USING A SACRIFICIAL CONDUCTIVE STACK TO PREVENT CORROSION

SELF-ALIGNED UNDER BUMP METAL

SELF-ALIGNED UNDER BUMP METAL

SELF-ALIGNED UNDER BUMP METAL

PROBE PAD DESIGN TO REDUCE SAW DEFECTS

Adhesion of Ferroelectric Material to Underlying Conductive Capacit...

HYDROGEN BARRIER FOR FERROELECTRIC CAPACITORS

HYDROGEN BARRIER FOR FERROELECTRIC CAPACITORS

ELECTROPLATED POSTS WITH REDUCED TOPOGRAPHY AND STRESS

HYDROGEN BARRIER FOR FERROELECTRIC CAPACITORS

LOW COST PROCESS FLOW FOR FABRICATION OF METAL CAPPING LAYER OVER C...

METHOD FOR PREPARING A METAL FEATURE SURFACE

Method for reducing integrated circuit defects

Method for reducing integrated circuit defects

ENHANCEMENT IN THROUGHPUT AND PLANARITY DURING CMP USING A DIELECTR...

Prevention of contact failure by hydrogen treatment

DIELECTRIC STRUCTURE AND METHOD FOR MINIMIZING EROSION DURING CHEMI...