Manoj Mehrotra

Person

Dallas, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Low leakage Schottky diode
- Patent number 11,532,758
- Issue date Dec 20, 2022
- Texas Instruments Incorporated
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor structure with silicided source and drain extensions and...
- Patent number 9,397,182
- Issue date Jul 19, 2016
- Texas Instruments Incorporated
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal-gate MOS transistor and method of forming the transistor with...
- Patent number 9,000,539
- Issue date Apr 7, 2015
- Texas Instruments Incorporated
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure that reduces the effects of gate cross diff...
- Patent number 8,906,770
- Issue date Dec 9, 2014
- Texas Instruments Incorporated
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor structure with silicided source and drain extensions and...
- Patent number 8,877,595
- Issue date Nov 4, 2014
- Texas Instruments Incorporated
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Trench with reduced silicon loss
- Patent number 8,691,661
- Issue date Apr 8, 2014
- Texas Instruments Incorporated
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Trenches with reduced silicon loss
- Patent number 8,685,831
- Issue date Apr 1, 2014
- Texas Instruments Incorporated
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of nitrogen containing dielectric layers having an improv...
- Patent number 8,617,954
- Issue date Dec 31, 2013
- Texas Instruments Incorporated
- Hiroaki Niimi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure that reduces the effects of gate cross diff...
- Patent number 8,592,902
- Issue date Nov 26, 2013
- Texas Instrument Incorporated
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
PMOS SiGe-last integration process
- Patent number 8,435,848
- Issue date May 7, 2013
- Texas Instruments Incorporated
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple indium implant methods and devices and integrated circuits...
- Patent number 7,960,238
- Issue date Jun 14, 2011
- Texas Instruments Incorporated
- Puneet Kohli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor doping with reduced gate edge diode leakage
- Patent number 7,897,496
- Issue date Mar 1, 2011
- Texas Instruments Incorporated
- Puneet Kohli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Use of poly resistor implant to dope poly gates
- Patent number 7,846,783
- Issue date Dec 7, 2010
- Texas Instruments Incorporated
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High threshold NMOS source-drain formation with As, P and C to redu...
- Patent number 7,736,983
- Issue date Jun 15, 2010
- Texas Instruments Incorporated
- Puneet Kohli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-stage implant to improve device characteristics
- Patent number 7,691,700
- Issue date Apr 6, 2010
- Texas Instruments Incorporated
- Manoj Mehrotra
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device made by using a laser anneal to incorporate st...
- Patent number 7,670,917
- Issue date Mar 2, 2010
- Texas Instruments Incorporated
- Amitabh Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Activation of CMOS source/drain extensions by ultra-high temperatur...
- Patent number 7,615,458
- Issue date Nov 10, 2009
- Texas Instruments Incorporated
- Amitabh Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device manufactured using a laminated stress layer
- Patent number 7,611,939
- Issue date Nov 3, 2009
- Texas Instruments Incorporated
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing an isolation structure using an energy bea...
- Patent number 7,524,777
- Issue date Apr 28, 2009
- Texas Instruments Incorporated
- Puneet Kohli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Slim spacer implementation to improve drive current
- Patent number 7,510,923
- Issue date Mar 31, 2009
- Texas Instruments Incorporated
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a gate sidewall spacer using an energy bea...
- Patent number 7,465,635
- Issue date Dec 16, 2008
- Texas Instruments Incorporated
- Puneet Kohli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing an integrated circuit using a capping laye...
- Patent number 7,344,929
- Issue date Mar 18, 2008
- Texas Instruments Incorporated
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow trench isolation method
- Patent number 7,279,397
- Issue date Oct 9, 2007
- Texas Instruments Incorporated
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method to strain NMOS devices while mitigating dopant diffusion for...
- Patent number 7,211,481
- Issue date May 1, 2007
- Texas Instruments Incorporated
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nitridation of STI liner oxide for modulating inverse width effects...
- Patent number 7,199,020
- Issue date Apr 3, 2007
- Texas Instruments Incorporated
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual salicide process for optimum performance
- Patent number 6,987,061
- Issue date Jan 17, 2006
- Texas Instruments Incorporated
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor with improved source/drain extension dopant concentration
- Patent number 6,743,705
- Issue date Jun 1, 2004
- Texas Instruments Incorporated
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and system for forming a transistor having source and drain...
- Patent number 6,737,325
- Issue date May 18, 2004
- Texas Instruments Incorporated
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sub-critical-dimension integrated circuit features
- Patent number 6,686,300
- Issue date Feb 3, 2004
- Texas Instruments Incorporated
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor with bottomwall/sidewall junction capacitance reduction...
- Patent number 6,677,208
- Issue date Jan 13, 2004
- Texas Instruments Incorporated
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
RAISED SOURCE/DRAIN TRANSISTOR
- Publication number 20240363434
- Publication date Oct 31, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW LEAKAGE SCHOTTKY DIODE
- Publication number 20230119046
- Publication date Apr 20, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIN TRANSISTORS WITH DOPED CONTROL LAYER FOR JUNCTION CONTROL
- Publication number 20220199828
- Publication date Jun 23, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIN-BASED LATERALLY-DIFFUSED METAL-OXIDE SEMICONDUCTOR FIELD EFFECT...
- Publication number 20220157972
- Publication date May 19, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SCHOTTKY DIODE
- Publication number 20210091237
- Publication date Mar 25, 2021
- TEXAS INSTRUMENTS INCORPORATED
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR STRUCTURE WITH SILICIDED SOURCE AND DRAIN EXTENSIONS AND...
- Publication number 20150008532
- Publication date Jan 8, 2015
- TEXAS INSTRUMENTS INCORPORATED
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRENCH WITH REDUCED SILICON LOSS
- Publication number 20140175597
- Publication date Jun 26, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Metal-Gate MOS Transistor and Method of Forming the Transistor with...
- Publication number 20140124874
- Publication date May 8, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE THAT REDUCES THE EFFECTS OF GATE CROSS DIFF...
- Publication number 20140087536
- Publication date Mar 27, 2014
- TEXAS INSTRUMENTS INCORPORATED
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Short-Resistant Metal-Gate MOS Transistor and Method of Forming the...
- Publication number 20130214289
- Publication date Aug 22, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRENCHES WITH REDUCED SILICON LOSS
- Publication number 20120104539
- Publication date May 3, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PMOS SiGe-LAST INTEGRATION PROCESS
- Publication number 20120108021
- Publication date May 3, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR STRUCTURE WITH SILICIDED SOURCE AND DRAIN EXTENSIONS AND...
- Publication number 20120104503
- Publication date May 3, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRENCH WITH REDUCED SILICON LOSS
- Publication number 20120104540
- Publication date May 3, 2012
- TEXAS INSTRUMENTS INCORPORATED
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIPLE INDIUM IMPLANT METHODS AND DEVICES AND INTEGRATED CIRCUITS...
- Publication number 20100164003
- Publication date Jul 1, 2010
- TEXAS INSTRUMENTS INCORPORATED
- PUNEET KOHLI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Use of Poly Resistor Implant to Dope Poly Gates
- Publication number 20100112764
- Publication date May 6, 2010
- TEXAS INSTRUMENTS INCORPORATED
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Slim Spacer Implementation to Improve Drive Current
- Publication number 20090184348
- Publication date Jul 23, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH THRESHOLD NMOS SOURCE-DRAIN FORMATION WITH As, P AND C TO REDU...
- Publication number 20090179280
- Publication date Jul 16, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Puneet Kohli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DOPING WITH REDUCED GATE EDGE DIODE LEAKAGE
- Publication number 20090127620
- Publication date May 21, 2009
- Puneet Kohli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FORMATION OF NITROGEN CONTAINING DIELECTRIC LAYERS HAVING AN IMPROV...
- Publication number 20090090990
- Publication date Apr 9, 2009
- Texas Instruments, Incorporated
- Hiroaki Niimi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device Made by Using a Laser Anneal to Incorporate St...
- Publication number 20090065880
- Publication date Mar 12, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Amitabh Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-STAGE IMPLANT TO IMPROVE DEVICE CHARACTERISTICS
- Publication number 20090004803
- Publication date Jan 1, 2009
- Manoj Mehrotra
- G11 - INFORMATION STORAGE
Information Patent Application
Activation of CMOS Source/Drain Extensions by Ultra-High Temperatur...
- Publication number 20080318387
- Publication date Dec 25, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Amitabh Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
P-DOPED REGION WITH IMPROVED ABRUPTNESS
- Publication number 20080308904
- Publication date Dec 18, 2008
- TEXAS INSTRUMENTS INCORPORATED
- P. R. Chidambaram
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor Device Manufactured Using a Laminated Stress Layer
- Publication number 20080277730
- Publication date Nov 13, 2008
- TEXAS INSTRUMENTS INCORPORATED
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
N-TYPE SEMICONDUCTOR COMPONENT WITH IMPROVED DOPANT IMPLANTATION PR...
- Publication number 20080268628
- Publication date Oct 30, 2008
- Puneet Kohli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming a recess in a semiconductor structure
- Publication number 20080233702
- Publication date Sep 25, 2008
- Texas Instruments Inc.
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High-stress liners for semiconductor fabrication
- Publication number 20080157292
- Publication date Jul 3, 2008
- Texas Instruments Inc.
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods and systems for nitridation of STI liner oxide in semicondu...
- Publication number 20080153256
- Publication date Jun 26, 2008
- Texas Instruments Inc.
- Hiroaki Niimi
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Slim spacer implementation to improve drive current
- Publication number 20080145991
- Publication date Jun 19, 2008
- Texas Instruments Inc.
- Manoj Mehrotra
- H01 - BASIC ELECTRIC ELEMENTS

Manoj Mehrotra

Person

Patents Grantslast 30 patents

Low leakage Schottky diode

Transistor structure with silicided source and drain extensions and...

Metal-gate MOS transistor and method of forming the transistor with...

Semiconductor structure that reduces the effects of gate cross diff...

Transistor structure with silicided source and drain extensions and...

Trench with reduced silicon loss

Trenches with reduced silicon loss

Formation of nitrogen containing dielectric layers having an improv...

Semiconductor structure that reduces the effects of gate cross diff...

PMOS SiGe-last integration process

Multiple indium implant methods and devices and integrated circuits...

Semiconductor doping with reduced gate edge diode leakage

Use of poly resistor implant to dope poly gates

High threshold NMOS source-drain formation with As, P and C to redu...

Multi-stage implant to improve device characteristics

Semiconductor device made by using a laser anneal to incorporate st...

Activation of CMOS source/drain extensions by ultra-high temperatur...

Semiconductor device manufactured using a laminated stress layer

Method for manufacturing an isolation structure using an energy bea...

Slim spacer implementation to improve drive current

Method for manufacturing a gate sidewall spacer using an energy bea...

Method for manufacturing an integrated circuit using a capping laye...

Shallow trench isolation method

Method to strain NMOS devices while mitigating dopant diffusion for...

Nitridation of STI liner oxide for modulating inverse width effects...

Dual salicide process for optimum performance

Transistor with improved source/drain extension dopant concentration

Method and system for forming a transistor having source and drain...

Sub-critical-dimension integrated circuit features

Transistor with bottomwall/sidewall junction capacitance reduction...

Patents Applicationslast 30 patents

RAISED SOURCE/DRAIN TRANSISTOR

LOW LEAKAGE SCHOTTKY DIODE

FIN TRANSISTORS WITH DOPED CONTROL LAYER FOR JUNCTION CONTROL

FIN-BASED LATERALLY-DIFFUSED METAL-OXIDE SEMICONDUCTOR FIELD EFFECT...

SCHOTTKY DIODE

TRANSISTOR STRUCTURE WITH SILICIDED SOURCE AND DRAIN EXTENSIONS AND...

TRENCH WITH REDUCED SILICON LOSS

Metal-Gate MOS Transistor and Method of Forming the Transistor with...

SEMICONDUCTOR STRUCTURE THAT REDUCES THE EFFECTS OF GATE CROSS DIFF...

Short-Resistant Metal-Gate MOS Transistor and Method of Forming the...

TRENCHES WITH REDUCED SILICON LOSS

PMOS SiGe-LAST INTEGRATION PROCESS

TRANSISTOR STRUCTURE WITH SILICIDED SOURCE AND DRAIN EXTENSIONS AND...

TRENCH WITH REDUCED SILICON LOSS

MULTIPLE INDIUM IMPLANT METHODS AND DEVICES AND INTEGRATED CIRCUITS...

Use of Poly Resistor Implant to Dope Poly Gates

Slim Spacer Implementation to Improve Drive Current

HIGH THRESHOLD NMOS SOURCE-DRAIN FORMATION WITH As, P AND C TO REDU...

SEMICONDUCTOR DOPING WITH REDUCED GATE EDGE DIODE LEAKAGE

FORMATION OF NITROGEN CONTAINING DIELECTRIC LAYERS HAVING AN IMPROV...

Semiconductor Device Made by Using a Laser Anneal to Incorporate St...

MULTI-STAGE IMPLANT TO IMPROVE DEVICE CHARACTERISTICS

Activation of CMOS Source/Drain Extensions by Ultra-High Temperatur...

P-DOPED REGION WITH IMPROVED ABRUPTNESS

Semiconductor Device Manufactured Using a Laminated Stress Layer

N-TYPE SEMICONDUCTOR COMPONENT WITH IMPROVED DOPANT IMPLANTATION PR...

Method of forming a recess in a semiconductor structure

High-stress liners for semiconductor fabrication

Methods and systems for nitridation of STI liner oxide in semicondu...

Slim spacer implementation to improve drive current