Masahiko Toyonaga

Person

Hyogo, JP

People

Patents Grantslast 30 patents

Information Patent Grant
High level synthesis method for semiconductor integrated circuit
- Patent number 7,237,220
- Issue date Jun 26, 2007
- Matsushita Electric Industrial Co., Ltd.
- Osamu Ogawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
LSI design system
- Patent number 7,100,136
- Issue date Aug 29, 2006
- Matsushita Electric Industrial Co., Ltd.
- Miwaka Takahashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay analysis method and design assist apparatus of semiconductor...
- Patent number 6,578,182
- Issue date Jun 10, 2003
- Matsushita Electric Industrial Co., Ltd.
- Keiichi Kurokawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for designing layout of semiconductor device, storage medium...
- Patent number 6,532,581
- Issue date Mar 11, 2003
- Matsushita Electric Industrial Co., Ltd.
- Masahiko Toyonaga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of optimizing placement of elements
- Patent number 6,499,133
- Issue date Dec 24, 2002
- Matsushita Electric Industrial Co., Ltd.
- Keiichi Kurokawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay analysis method and design assist apparatus of semiconductor...
- Patent number 6,496,963
- Issue date Dec 17, 2002
- Matsushita Electric Industrial Co., Ltd.
- Keiichi Kurokawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock circuit and method of designing the same
- Patent number 6,473,890
- Issue date Oct 29, 2002
- Takuya Yasui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
LSI design system
- Patent number 6,415,423
- Issue date Jul 2, 2002
- Matsushita Electric Industrial Co., Ltd.
- Miwaka Takahashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor integrated circuit and manufacturing method therefor,...
- Patent number 6,367,061
- Issue date Apr 2, 2002
- Matsushita Electric Industrial Co., Ltd.
- Keiichi Kurokawa
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for designing semiconductor integrated circuit
- Patent number 6,336,205
- Issue date Jan 1, 2002
- Matsushita Electric Industrial Co., Ltd.
- Keiichi Kurokawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for optimizing component placement in designing a semiconduc...
- Patent number 6,263,475
- Issue date Jul 17, 2001
- Matsushita Electric Industrial Co., Ltd.
- Masahiko Toyonaga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic synthesizing method for logic circuits
- Patent number 6,096,092
- Issue date Aug 1, 2000
- Matsushita Electric Industrial Co., Ltd.
- Miwaka Takahashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor integrated circuit capable of compensating for flucua...
- Patent number 6,000,829
- Issue date Dec 14, 1999
- Matsushita Electric Industrial Co., Ltd.
- Keiichi Kurokawa
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
LSI layout design method capable of satisfying timing requirements...
- Patent number 5,999,716
- Issue date Dec 7, 1999
- Matsushita Electric Industrial Co., Ltd.
- Masahiko Toyonaga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
LSI wire length estimation and area estimation
- Patent number 5,978,572
- Issue date Nov 2, 1999
- Matsushita Electric Industrial Co., Ltd.
- Masahiko Toyonaga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for automating top-down design processing for the design of...
- Patent number 5,963,730
- Issue date Oct 5, 1999
- Matsushita Electric Industrial Co., Ltd.
- Masahiko Toyonaga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock distribution circuit with clock branch circuits connected to...
- Patent number 5,896,055
- Issue date Apr 20, 1999
- Matsushita Electronic Industrial Co., Ltd.
- Masahiko Toyonaga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for designing an LSI layout utilizing cells ha...
- Patent number 5,852,562
- Issue date Dec 22, 1998
- Matsushita Electric Industrial Co., Ltd.
- Noriko Shinomiya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic synthesis method and logic synthesis apparatus
- Patent number 5,673,200
- Issue date Sep 30, 1997
- Matsushita Electric Industrial Co., Ltd.
- Masahiko Toyonaga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for automatically arranging circuit elements i...
- Patent number 5,657,243
- Issue date Aug 12, 1997
- Matsushita Electric Industrial Co., Ltd.
- Masahiko Toyonaga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for classifying and evaluating logic circuit
- Patent number 5,490,083
- Issue date Feb 6, 1996
- Matsushita Electric Industrial Co., Ltd.
- Masahiko Toyonaga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for sorting count information by summing frequenc...
- Patent number 5,479,657
- Issue date Dec 26, 1995
- Matsushita Electric Industrial Co., Ltd.
- Masahiko Toyonaga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Channel routing method
- Patent number 5,272,645
- Issue date Dec 21, 1993
- Matsushita Electric Industrial Co., Ltd.
- Yoshiyuki Kawakami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for VLSI layout pattern compaction by using direct access me...
- Patent number 5,267,177
- Issue date Nov 30, 1993
- Matsushita Electric Industrial Co., Ltd.
- Koichi Sato
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement optimization system aided by CAD
- Patent number 5,187,668
- Issue date Feb 16, 1993
- Matsushita Electric Industrial Co., Ltd.
- Hiroaki Okude
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for optimizing a physical organization of elements of an int...
- Patent number 5,159,682
- Issue date Oct 27, 1992
- Matsushita Electric Industrial Co., Ltd.
- Masahiko Toyonaga
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
High level synthesis method for semiconductor integrated circuit
- Publication number 20050289499
- Publication date Dec 29, 2005
- MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- Osamu Ogawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Delay analysis method and design assist apparatus of semiconductor...
- Publication number 20030070151
- Publication date Apr 10, 2003
- Matsushita Electric Industrial Co., Ltd.
- Keiichi Kurokawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LSI design system
- Publication number 20020162080
- Publication date Oct 31, 2002
- MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- Miwaka Takahashi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Delay analysis method and design assist apparatus of semiconductor...
- Publication number 20020010900
- Publication date Jan 24, 2002
- Keiichi Kurokawa
- G06 - COMPUTING CALCULATING COUNTING

Masahiko Toyonaga

Person

Patents Grantslast 30 patents

High level synthesis method for semiconductor integrated circuit

LSI design system

Delay analysis method and design assist apparatus of semiconductor...

Method for designing layout of semiconductor device, storage medium...

Method of optimizing placement of elements

Delay analysis method and design assist apparatus of semiconductor...

Clock circuit and method of designing the same

LSI design system

Semiconductor integrated circuit and manufacturing method therefor,...

Method for designing semiconductor integrated circuit

Method for optimizing component placement in designing a semiconduc...

Automatic synthesizing method for logic circuits

Semiconductor integrated circuit capable of compensating for flucua...

LSI layout design method capable of satisfying timing requirements...

LSI wire length estimation and area estimation

Method for automating top-down design processing for the design of...

Clock distribution circuit with clock branch circuits connected to...

Method and apparatus for designing an LSI layout utilizing cells ha...

Logic synthesis method and logic synthesis apparatus

Method and apparatus for automatically arranging circuit elements i...

Method and apparatus for classifying and evaluating logic circuit

System and method for sorting count information by summing frequenc...

Channel routing method

Method for VLSI layout pattern compaction by using direct access me...

Placement optimization system aided by CAD

System for optimizing a physical organization of elements of an int...

Patents Applicationslast 30 patents

High level synthesis method for semiconductor integrated circuit

Delay analysis method and design assist apparatus of semiconductor...

LSI design system

Delay analysis method and design assist apparatus of semiconductor...