Masahiro Fukui

Person

Ibaraki-shi, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Delay distribution calculation method, circuit evaluation method an...
- Patent number 7,131,082
- Issue date Oct 31, 2006
- Matsushita Electric Industrial Co., Ltd.
- Shuji Tsukiyama
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-pass filter for a PLL, phase-locked loop and semiconductor inte...
- Patent number 7,030,688
- Issue date Apr 18, 2006
- Matsushita Electric Industrial Co., Ltd.
- Shiro Dosho
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of physical design for integrated circuit
- Patent number 6,769,098
- Issue date Jul 27, 2004
- Matsushita Electric Industrial Co., Ltd.
- Masakazu Tanaka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wiring method in layout design of semiconductor integrated circuit,...
- Patent number 6,727,120
- Issue date Apr 27, 2004
- Matsushita Electric Industrial Co., Ltd.
- Masahiro Fukui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Delay distribution calculation method, circuit evaluation method an...
- Patent number 6,684,375
- Issue date Jan 27, 2004
- Matsushita Electric Industrial Co., Ltd.
- Shuji Tsukiyama
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Routing path finding method for automated routing/designing process...
- Patent number 6,609,237
- Issue date Aug 19, 2003
- Matsushita Electric Industrial Co., Ltd.
- Koji Hamawaki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for design of partial circuit
- Patent number 6,553,544
- Issue date Apr 22, 2003
- Matsushita Electric Industrial Co., Ltd.
- Masakazu Tanaka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout structure for integrated circuit, method and system for gene...
- Patent number 6,516,458
- Issue date Feb 4, 2003
- Matsushita Electric Industrial Co., Ltd.
- Masahiro Fukui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for transistor optimization, method and appara...
- Patent number 6,415,417
- Issue date Jul 2, 2002
- Matsushita Electric Industrial Co., Ltd.
- Masakazu Tanaka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout designing apparatus for integrated circuit, transistor size...
- Patent number 6,393,601
- Issue date May 21, 2002
- Matsushita Electric Industrial Co., Ltd.
- Masakazu Tanaka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for designing LSI layout, cell library for des...
- Patent number 6,336,207
- Issue date Jan 1, 2002
- Matsushita Electric Industrial Co., Ltd.
- Noriko Shinomiya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic routing method
- Patent number 6,330,707
- Issue date Dec 11, 2001
- Matsushita Electric Industrial Co., Ltd.
- Noriko Shinomiya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Functional module model, pipelined circuit synthesis and pipelined...
- Patent number 6,292,926
- Issue date Sep 18, 2001
- Matsushita Electric Industrial Co., Ltd.
- Masahiro Fukui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit optimization system
- Patent number 6,253,351
- Issue date Jun 26, 2001
- Matsushita Electric Industrial Co., Ltd.
- Masahiro Fukui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for synthesizing module
- Patent number 6,209,119
- Issue date Mar 27, 2001
- Matsushita Electric Industrial Co., Ltd.
- Masahiro Fukui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor integrated circuit layout method
- Patent number 6,202,195
- Issue date Mar 13, 2001
- Matsushita Electric Industrial Co., Ltd.
- Masakazu Tanaka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compaction method, compaction apparatus, routing method and routing...
- Patent number 5,943,486
- Issue date Aug 24, 1999
- Matsushita Electric Industrial Co.,Ltd.
- Masahiro Fukui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for designing an LSI layout utilizing cells ha...
- Patent number 5,852,562
- Issue date Dec 22, 1998
- Matsushita Electric Industrial Co., Ltd.
- Noriko Shinomiya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cell generation method and cell generation system
- Patent number 5,701,255
- Issue date Dec 23, 1997
- Matsushita Electric Industrial Co., Ltd.
- Masahiro Fukui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor apparatus and production method for the same
- Patent number 5,677,249
- Issue date Oct 14, 1997
- Matsushita Electric Industrial Co., Ltd.
- Masahiro Fukui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for estimating power dissipation and method an...
- Patent number 5,602,753
- Issue date Feb 11, 1997
- Matsushita Electric Industrial Co., Ltd.
- Masahiro Fukui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout method for a semiconductor integrated circuit device
- Patent number 5,420,800
- Issue date May 30, 1995
- Matsushita Electric Industrial Co., Ltd.
- Masahiro Fukui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for optimizing block shape in hierarchical IC...
- Patent number 5,416,720
- Issue date May 16, 1995
- Matsushita Electric Industrial Co., Ltd.
- Masahiro Fukui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for assigning positions of block terminals in a VLSI
- Patent number 5,404,313
- Issue date Apr 4, 1995
- Matsushita Electric Industrial Co., Ltd.
- Takahiro Shiohara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
L-shaped channel wiring method
- Patent number 5,241,455
- Issue date Aug 31, 1993
- Matsushita Electric Industrial Co., Ltd.
- Masahiro Fukui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layout pattern generation and geometric processing system for LSI c...
- Patent number 5,062,054
- Issue date Oct 29, 1991
- Matsushita Electric Industrial Co., Ltd.
- Yoshiyuki Kawakami
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Building block LSI
- Patent number 4,875,139
- Issue date Oct 17, 1989
- Matsushita Electric Industrial Co., Ltd.
- Masahiro Fukui
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Delay distribution calculation method, circuit evaluation method an...
- Publication number 20070033554
- Publication date Feb 8, 2007
- Matsushita Electric Industrial Co., Ltd.
- Shuji Tsukiyama
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Low-pass filter for a pll, phase-locked loop and semiconductor inte...
- Publication number 20050077955
- Publication date Apr 14, 2005
- Shiro Dosho
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Wiring method in layout design of semiconductor integrated circuit,...
- Publication number 20040181766
- Publication date Sep 16, 2004
- Matsushita Electric Industrial Co., Ltd.
- Masahiro Fukui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Delay distribution calculation method, circuit evaluation method an...
- Publication number 20040132224
- Publication date Jul 8, 2004
- Matsushita Electric Industrial Co., Ltd.
- Shuji Tsukiyama
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuit operation simulating apparatus
- Publication number 20040107087
- Publication date Jun 3, 2004
- MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- Masahiro Fukui
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Wiring method in layout design of semiconductor integrated circuit,...
- Publication number 20020127782
- Publication date Sep 12, 2002
- MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- Masahiro Fukui
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Delay distribution calculation method, circuit evaluation method an...
- Publication number 20020104065
- Publication date Aug 1, 2002
- MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- Shuji Tsukiyama
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR DESIGNING LSI LAYOUT, CELL LIBRARY FOR DES...
- Publication number 20010049815
- Publication date Dec 6, 2001
- NORIKO SHINOMIYA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for design of partial circuit
- Publication number 20010027553
- Publication date Oct 4, 2001
- Masakazu Tanaka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of physical design for integrated circuit
- Publication number 20010018758
- Publication date Aug 30, 2001
- MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
- Masakazu Tanaka
- G06 - COMPUTING CALCULATING COUNTING

Masahiro Fukui

Person

Patents Grantslast 30 patents

Delay distribution calculation method, circuit evaluation method an...

Low-pass filter for a PLL, phase-locked loop and semiconductor inte...

Method of physical design for integrated circuit

Wiring method in layout design of semiconductor integrated circuit,...

Delay distribution calculation method, circuit evaluation method an...

Routing path finding method for automated routing/designing process...

Method for design of partial circuit

Layout structure for integrated circuit, method and system for gene...

Method and apparatus for transistor optimization, method and appara...

Layout designing apparatus for integrated circuit, transistor size...

Method and apparatus for designing LSI layout, cell library for des...

Automatic routing method

Functional module model, pipelined circuit synthesis and pipelined...

Circuit optimization system

Apparatus and method for synthesizing module

Semiconductor integrated circuit layout method

Compaction method, compaction apparatus, routing method and routing...

Method and apparatus for designing an LSI layout utilizing cells ha...

Cell generation method and cell generation system

Semiconductor apparatus and production method for the same

Method and apparatus for estimating power dissipation and method an...

Layout method for a semiconductor integrated circuit device

Method and apparatus for optimizing block shape in hierarchical IC...

System for assigning positions of block terminals in a VLSI

L-shaped channel wiring method

Layout pattern generation and geometric processing system for LSI c...

Building block LSI

Patents Applicationslast 30 patents

Delay distribution calculation method, circuit evaluation method an...

Low-pass filter for a pll, phase-locked loop and semiconductor inte...

Wiring method in layout design of semiconductor integrated circuit,...

Delay distribution calculation method, circuit evaluation method an...

Circuit operation simulating apparatus

Wiring method in layout design of semiconductor integrated circuit,...

Delay distribution calculation method, circuit evaluation method an...

METHOD AND APPARATUS FOR DESIGNING LSI LAYOUT, CELL LIBRARY FOR DES...

Method for design of partial circuit

Method of physical design for integrated circuit