Masakazu Shoji

Person

Warren, NJ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Process-tolerant integrated circuit design
- Patent number 6,496,056
- Issue date Dec 17, 2002
- Agere Systems Inc.
- Masakazu Shoji
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Unidirectionality in electronic circuits through feedback
- Patent number 6,366,074
- Issue date Apr 2, 2002
- Agere Systems Guardian Corp.
- Masakazu Shoji
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital signal transition edge alignment using interacting inverter...
- Patent number 5,959,480
- Issue date Sep 28, 1999
- Lucent Technologies Inc.
- Masakazu Shoji
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory chip architecture and packaging method for increased product...
- Patent number 5,793,942
- Issue date Aug 11, 1998
- Lucent Technologies Inc.
- Masakazu Shoji
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor optical storage device and uses thereof
- Patent number 5,786,827
- Issue date Jul 28, 1998
- Lucent Technologies Inc.
- Milan F. Jukl
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-density read-only memory
- Patent number 5,598,365
- Issue date Jan 28, 1997
- Lucent Technologies Inc.
- Masakazu Shoji
- G11 - INFORMATION STORAGE
Information Patent Grant
Fixed-interval timing circuit and method
- Patent number 5,578,952
- Issue date Nov 26, 1996
- Lucent Technologies Inc.
- Masakazu Shoji
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High-density read-only memory employing multiple bit-line interconn...
- Patent number 5,528,534
- Issue date Jun 18, 1996
- AT&T Corp.
- Masakazu Shoji
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit memory device
- Patent number 5,499,208
- Issue date Mar 12, 1996
- AT&T Corp.
- Masakazu Shoji
- G11 - INFORMATION STORAGE
Information Patent Grant
High-density read-only memory fabrication
- Patent number 5,418,178
- Issue date May 23, 1995
- AT&T Corp.
- Masakazu Shoji
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuits which compensate for local conditions
- Patent number 5,117,130
- Issue date May 26, 1992
- AT&T Bell Laboratories
- Masakazu Shoji
- G05 - CONTROLLING REGULATING
Information Patent Grant
Apparatus including resonant-tunneling device having multiple-peak...
- Patent number 4,902,912
- Issue date Feb 20, 1990
- American Telephone and Telegraph Company, AT&T Bell Laboratories
- Federico Capasso
- B82 - NANO-TECHNOLOGY
Information Patent Grant
CMOS Integrated circuit digital crossbar switching arrangement
- Patent number 4,849,751
- Issue date Jul 18, 1989
- American Telephone and Telegraph Company, AT&T Bell Laboratories
- Frank E. Barber
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High speed MOS circuits
- Patent number 4,782,253
- Issue date Nov 1, 1988
- American Telephone and Telegraph Company, AT&T Bell Laboratories
- Masakazu Shoji
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dual domino CMOS logic circuit, including complementary vectorizati...
- Patent number 4,710,650
- Issue date Dec 1, 1987
- American Telephone and Telegraph Company, AT&T Bell Laboratories
- Masakazu Shoji
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
CMOS logic circuit with single clock pulse
- Patent number 4,692,637
- Issue date Sep 8, 1987
- AT&T Bell Laboratories
- Masakazu Shoji
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit arrangement for controlling threshold voltages in CMOS circ...
- Patent number 4,670,670
- Issue date Jun 2, 1987
- American Telephone and Telegraph Company AT&T Bell Laboratories
- Masakazu Shoji
- G05 - CONTROLLING REGULATING
Information Patent Grant
Chain logic scheme for programmed logic array
- Patent number 4,668,880
- Issue date May 26, 1987
- American Telephone and Telegraph Company, AT&T Bell Laboratories
- Masakazu Shoji
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Synthetic CMOS static logic gates
- Patent number 4,649,296
- Issue date Mar 10, 1987
- AT&T Bell Laboratories
- Masakazu Shoji
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
IC chip with noise suppression circuit
- Patent number 4,585,958
- Issue date Apr 29, 1986
- AT&T Bell Laboratories
- Michael S. Chung
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
CMOS Logic circuits with all pull-up transistors integrated in sepa...
- Patent number 4,572,972
- Issue date Feb 25, 1986
- AT&T Laboratories
- Masakazu Shoji
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit including logic array with distributed ground co...
- Patent number 4,516,123
- Issue date May 7, 1985
- AT&T Bell Laboratories
- Masakazu Shoji
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Chipset synchronization arrangement
- Patent number 4,514,647
- Issue date Apr 30, 1985
- AT&T Bell Laboratories
- Masakazu Shoji
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
VLSI Chip with ground shielding
- Patent number 4,514,749
- Issue date Apr 30, 1985
- AT&T Bell Laboratories
- Masakazu Shoji
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Databus coupling arrangement using transistors of complementary con...
- Patent number 4,488,066
- Issue date Dec 11, 1984
- AT&T Bell Laboratories
- Masakazu Shoji
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Skew-free clock circuit for integrated circuit chip
- Patent number 4,479,216
- Issue date Oct 23, 1984
- AT&T Bell Laboratories
- Robert H. Krambeck
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Single terminal negative capacitance generator for response time en...
- Patent number 4,443,882
- Issue date Apr 17, 1984
- Bell Telephone Laboratories, Incorporated
- Robert M. Rolfe
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus for increasing the speed of a circuit having a string of...
- Patent number 4,430,583
- Issue date Feb 7, 1984
- Bell Telephone Laboratories, Incorporated
- Masakazu Shoji
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Microprocessor architecture for improved chip testability
- Patent number 4,422,141
- Issue date Dec 20, 1983
- Bell Telephone Laboratories, Incorporated
- Masakazu Shoji
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor architecture having internal access means
- Patent number 4,403,287
- Issue date Sep 6, 1983
- Bell Telephone Laboratories, Incorporated
- Donald E. Blahut
- G06 - COMPUTING CALCULATING COUNTING

Masakazu Shoji

Person

Patents Grantslast 30 patents

Process-tolerant integrated circuit design

Unidirectionality in electronic circuits through feedback

Digital signal transition edge alignment using interacting inverter...

Memory chip architecture and packaging method for increased product...

Semiconductor optical storage device and uses thereof

High-density read-only memory

Fixed-interval timing circuit and method

High-density read-only memory employing multiple bit-line interconn...

Integrated circuit memory device

High-density read-only memory fabrication

Integrated circuits which compensate for local conditions

Apparatus including resonant-tunneling device having multiple-peak...

CMOS Integrated circuit digital crossbar switching arrangement

High speed MOS circuits

Dual domino CMOS logic circuit, including complementary vectorizati...

CMOS logic circuit with single clock pulse

Circuit arrangement for controlling threshold voltages in CMOS circ...

Chain logic scheme for programmed logic array

Synthetic CMOS static logic gates

IC chip with noise suppression circuit

CMOS Logic circuits with all pull-up transistors integrated in sepa...

Integrated circuit including logic array with distributed ground co...

Chipset synchronization arrangement

VLSI Chip with ground shielding

Databus coupling arrangement using transistors of complementary con...

Skew-free clock circuit for integrated circuit chip

Single terminal negative capacitance generator for response time en...

Apparatus for increasing the speed of a circuit having a string of...

Microprocessor architecture for improved chip testability

Microprocessor architecture having internal access means