Matthew S. Buynoski

Person

Palo Alto, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method of forming controllably conductive oxide
- Patent number 10,147,877
- Issue date Dec 4, 2018
- Cypress Semiconductor Corporation
- Matthew Buynoski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming controllably conductive oxide
- Patent number 9,461,247
- Issue date Oct 4, 2016
- Cypress Semiconductor Corporation
- Matthew Buynoski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming controllably conductive oxide
- Patent number 8,946,020
- Issue date Feb 3, 2015
- Spansion, LLC
- Matthew Buynoski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buried silicide local interconnect with sidewall spacers and method...
- Patent number 8,368,219
- Issue date Feb 5, 2013
- Advanced Micro Devices, Inc.
- Arvind Halliyal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gettering/stop layer for prevention of reduction of insulating oxid...
- Patent number 8,093,698
- Issue date Jan 10, 2012
- Spansion LLC
- Manuj Rathor
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test structures for development of metal-insulator-metal (MIM) devices
- Patent number 8,084,770
- Issue date Dec 27, 2011
- Spansion LLC
- Steven Avanzino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buried silicide local interconnect with sidewall spacers and method...
- Patent number 8,049,334
- Issue date Nov 1, 2011
- Advanced Micro Devices, Inc.
- Arvind Halliyal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device built on plastic substrate
- Patent number 8,044,387
- Issue date Oct 25, 2011
- Spansion LLC
- Matthew S. Buynoski
- G11 - INFORMATION STORAGE
Information Patent Grant
Processing a copolymer to form a polymer memory cell
- Patent number 8,012,673
- Issue date Sep 6, 2011
- Spansion LLC
- Suzette K. Pangrle
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buried silicide local interconnect with sidewall spacers and method...
- Patent number 7,786,003
- Issue date Aug 31, 2010
- Advanced Micro Devices, Inc.
- Arvind Halliyal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FinFET device with multiple fin structures
- Patent number 7,679,134
- Issue date Mar 16, 2010
- GlobalFoundries
- Matthew S. Buynoski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thin film germanium diode with low reverse breakdown
- Patent number 7,468,296
- Issue date Dec 23, 2008
- Spansion LLC
- Ercan Adem
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test structures for development of metal-insulator-metal (MIM) devices
- Patent number 7,468,525
- Issue date Dec 23, 2008
- Spansion LLC
- Steven Avanzino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
FinFET device with multiple channels
- Patent number 7,432,557
- Issue date Oct 7, 2008
- Advanced Micro Devices, Inc.
- Matthew S. Buynoski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon on insulator field effect transistor with heterojunction gate
- Patent number 7,105,421
- Issue date Sep 12, 2006
- Advanced Micro Devices, Inc.
- Qi Xiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ion path polymers for ion-motion memory
- Patent number 7,067,349
- Issue date Jun 27, 2006
- Spansion LLC
- Matthew S. Buynoski
- G11 - INFORMATION STORAGE
Information Patent Grant
Diode array architecture for addressing nanoscale resistive memory...
- Patent number 7,035,141
- Issue date Apr 25, 2006
- Spansion LLC
- Nicholas H. Tripsas
- G11 - INFORMATION STORAGE
Information Patent Grant
Self aligned damascene gate
- Patent number 7,029,958
- Issue date Apr 18, 2006
- Advanced Micro Devices, Inc.
- Cyrus E. Tabery
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Implanted barrier layer to improve line reliability and method of f...
- Patent number 6,992,004
- Issue date Jan 31, 2006
- Advanced Micro Devices, Inc.
- Paul R. Besser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of self-annealing conductive lines that separates grain size...
- Patent number 6,979,642
- Issue date Dec 27, 2005
- Advanced Micro Devices, Inc.
- Matthew S. Buynoski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Planar polymer memory device
- Patent number 6,977,389
- Issue date Dec 20, 2005
- Advanced Micro Devices, Inc.
- Nicholas H. Tripsas
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for manufacturing a memory element
- Patent number 6,916,696
- Issue date Jul 12, 2005
- Advanced Micro Devices, Inc.
- Matthew S. Buynoski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CuS formation by anodic sulfide passivation of copper surface
- Patent number 6,893,895
- Issue date May 17, 2005
- Advanced Micro Devices, Inc.
- Uzodinma Okoroanyanwu
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Grant
Semiconductor device with non-compounded contacts, and method of ma...
- Patent number 6,872,644
- Issue date Mar 29, 2005
- Advanced Micro Devices, Inc.
- Matthew S. Buynoski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for fabricating CMOS-compatible lateral bipolar junction tr...
- Patent number 6,861,325
- Issue date Mar 1, 2005
- Advanced Micro Devices, Inc.
- James N. Pan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming an adhesion layer with an element reactive with a...
- Patent number 6,861,349
- Issue date Mar 1, 2005
- Advanced Micro Devices, Inc.
- Sergey D. Lopatin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self assembly of conducting polymer for formation of polymer memory...
- Patent number 6,852,586
- Issue date Feb 8, 2005
- Advanced Micro Devices, Inc.
- Matthew S. Buynoski
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of implanting copper barrier material to improve electrical...
- Patent number 6,835,655
- Issue date Dec 28, 2004
- Advanced Micro Devices, Inc.
- Paul R. Besser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming an electroless nucleation layer on a via bottom
- Patent number 6,815,340
- Issue date Nov 9, 2004
- Advanced Micro Devices, Inc.
- Sergey D. Lopatin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon containing material for patterning polymeric memory element
- Patent number 6,803,267
- Issue date Oct 12, 2004
- Advanced Micro Devices, Inc.
- Ramkumar Subramanian
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Method of forming controllably conductive oxide
- Publication number 20160380195
- Publication date Dec 29, 2016
- CYPRESS SEMICONDUCTOR CORPORATION
- Matthew BUYNOSKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING CONTROLLABLY CONDUCTIVE OXIDE
- Publication number 20150144857
- Publication date May 28, 2015
- SPANSION LLC
- Matthew BUYNOSKI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BURIED SILICIDE LOCAL INTERCONNECT WITH SIDEWALL SPACERS AND METHOD...
- Publication number 20120038051
- Publication date Feb 16, 2012
- SPANSION LLC
- Arvind Halliyal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Test Stuctures for development of metal-insulator-metal (MIM) devices
- Publication number 20090072234
- Publication date Mar 19, 2009
- Steven Avanzino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming controllably conductive oxide
- Publication number 20090067213
- Publication date Mar 12, 2009
- Matthew Buynoski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Ta-lined tungsten plugs for transistor-local hydrogen gathering
- Publication number 20090065842
- Publication date Mar 12, 2009
- Matthew Buynoski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Gettering/stop layer for prevention of reduction of insulating oxid...
- Publication number 20080130195
- Publication date Jun 5, 2008
- Spansion LLC
- Manuj Rathor
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Test structures for development of metal-insulator-metal (MIM) devices
- Publication number 20080128691
- Publication date Jun 5, 2008
- Spansion LLC
- Steven Avanzino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIODE ARRAY ARCHITECTURE FOR ADDRESSING NANOSCALE RESISTIVE MEMORY...
- Publication number 20060104111
- Publication date May 18, 2006
- Spansion LLC
- Nicholas H. Tripsas
- G11 - INFORMATION STORAGE
Information Patent Application
Self aligned damascene gate
- Publication number 20050104091
- Publication date May 19, 2005
- Cyrus E. Tabery
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Planar polymer memory device
- Publication number 20040238864
- Publication date Dec 2, 2004
- Nicholas H. Tripsas
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF IMPLANTATION AFTER COPPER SEED DEPOSITION
- Publication number 20040023486
- Publication date Feb 5, 2004
- Advanced Micro Devices, Inc.
- Sergey D. Lopatin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Self-aligned triple gate silicon-on-insulator (SOI) device
- Publication number 20030136963
- Publication date Jul 24, 2003
- Advanced Micro Devices, Inc.
- Zoran Krivokapic
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IMPROVED SILICIDE PROCESS USING HIGH K-DIELECTRICS
- Publication number 20030042515
- Publication date Mar 6, 2003
- Advanced Micro Devices, Inc.
- Qi Xiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Silicide stop layer in a damascene semiconductor structure
- Publication number 20030034533
- Publication date Feb 20, 2003
- Advanced Micro Devices, Inc.
- Eric N. Paton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
XE preamorphizing implantation
- Publication number 20030027381
- Publication date Feb 6, 2003
- Advanced Micro Devices, Inc.
- Matthew Stephen Buynoski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Silicon on insulator field effect transistor with heterojunction gate
- Publication number 20030011030
- Publication date Jan 16, 2003
- Qi Xiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non-arsenic N-type dopant implantation for improved source/drain in...
- Publication number 20020146904
- Publication date Oct 10, 2002
- Advanced Micro Devices, Inc.
- Matthew S. Buynoski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Damascene nisi metal gate high-k transistor
- Publication number 20020102848
- Publication date Aug 1, 2002
- Advanced Micro Devices, Inc.
- Qi Xiang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING NICKEL SILICIDE USING A ONE-STEP RAPID THERMAL AN...
- Publication number 20020068408
- Publication date Jun 6, 2002
- Advanced Micro Devices, Inc.
- Eric N. Paton
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25U AND SMALLER SEMI...
- Publication number 20020003306
- Publication date Jan 10, 2002
- MINH VAN NGO
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH-K GATE DIELECTRIC PROCESS WITH SELF ALIGNED DAMASCENE CONTACT...
- Publication number 20010053594
- Publication date Dec 20, 2001
- QI XIANG
- H01 - BASIC ELECTRIC ELEMENTS

Matthew S. Buynoski

Person

Patents Grantslast 30 patents

Method of forming controllably conductive oxide

Method of forming controllably conductive oxide

Method of forming controllably conductive oxide

Buried silicide local interconnect with sidewall spacers and method...

Gettering/stop layer for prevention of reduction of insulating oxid...

Test structures for development of metal-insulator-metal (MIM) devices

Buried silicide local interconnect with sidewall spacers and method...

Semiconductor device built on plastic substrate

Processing a copolymer to form a polymer memory cell

Buried silicide local interconnect with sidewall spacers and method...

FinFET device with multiple fin structures

Thin film germanium diode with low reverse breakdown

Test structures for development of metal-insulator-metal (MIM) devices

FinFET device with multiple channels

Silicon on insulator field effect transistor with heterojunction gate

Ion path polymers for ion-motion memory

Diode array architecture for addressing nanoscale resistive memory...

Self aligned damascene gate

Implanted barrier layer to improve line reliability and method of f...

Method of self-annealing conductive lines that separates grain size...

Planar polymer memory device

Method for manufacturing a memory element

CuS formation by anodic sulfide passivation of copper surface

Semiconductor device with non-compounded contacts, and method of ma...

Methods for fabricating CMOS-compatible lateral bipolar junction tr...

Method of forming an adhesion layer with an element reactive with a...

Self assembly of conducting polymer for formation of polymer memory...

Method of implanting copper barrier material to improve electrical...

Method of forming an electroless nucleation layer on a via bottom

Silicon containing material for patterning polymeric memory element

Patents Applicationslast 30 patents

Method of forming controllably conductive oxide

METHOD OF FORMING CONTROLLABLY CONDUCTIVE OXIDE

BURIED SILICIDE LOCAL INTERCONNECT WITH SIDEWALL SPACERS AND METHOD...

Test Stuctures for development of metal-insulator-metal (MIM) devices

Method of forming controllably conductive oxide

Ta-lined tungsten plugs for transistor-local hydrogen gathering

Gettering/stop layer for prevention of reduction of insulating oxid...

Test structures for development of metal-insulator-metal (MIM) devices

DIODE ARRAY ARCHITECTURE FOR ADDRESSING NANOSCALE RESISTIVE MEMORY...

Self aligned damascene gate

Planar polymer memory device

METHOD OF IMPLANTATION AFTER COPPER SEED DEPOSITION

Self-aligned triple gate silicon-on-insulator (SOI) device

IMPROVED SILICIDE PROCESS USING HIGH K-DIELECTRICS

Silicide stop layer in a damascene semiconductor structure

XE preamorphizing implantation

Silicon on insulator field effect transistor with heterojunction gate

Non-arsenic N-type dopant implantation for improved source/drain in...

Damascene nisi metal gate high-k transistor

METHOD OF FORMING NICKEL SILICIDE USING A ONE-STEP RAPID THERMAL AN...

METHOD FOR REDUCING STRESS-INDUCED VOIDS FOR 0.25U AND SMALLER SEMI...

HIGH-K GATE DIELECTRIC PROCESS WITH SELF ALIGNED DAMASCENE CONTACT...