Mehul D. Shroff

Person

Austin, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Packaged integrated circuit having a photodiode and a resistive memory
- Patent number 11,222,679
- Issue date Jan 11, 2022
- NXP USA, INC.
- Nihaar N. Mahatme
- G11 - INFORMATION STORAGE
Information Patent Grant
Magnetic attack detection in a magnetic random access memory (MRAM)
- Patent number 10,921,390
- Issue date Feb 16, 2021
- NXP USA, INC.
- Nihaar N. Mahatme
- G11 - INFORMATION STORAGE
Information Patent Grant
Post contact air gap formation
- Patent number 10,510,616
- Issue date Dec 17, 2019
- NXP USA, INC.
- Mehul D. Shroff
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming inter-level dielectric structures on semiconducto...
- Patent number 10,262,893
- Issue date Apr 16, 2019
- NXP USA, INC.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with graphene encapsulated metal and method th...
- Patent number 10,204,860
- Issue date Feb 12, 2019
- NXP USA, INC.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multigate transistor
- Patent number 10,103,241
- Issue date Oct 16, 2018
- NXP USA, INC.
- Douglas Michael Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Safe operating area checking method and apparatus
- Patent number 10,041,993
- Issue date Aug 7, 2018
- NXP USA, INC.
- Xavier Hours
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Substrate contacts for a transistor
- Patent number 10,038,081
- Issue date Jul 31, 2018
- NXP USA, INC.
- Douglas Michael Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and method for placing stressors within an integrated cir...
- Patent number 10,014,257
- Issue date Jul 3, 2018
- NXP USA, INC.
- Douglas M. Reber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Solar cell powered integrated circuit device and method therefor
- Patent number 10,008,447
- Issue date Jun 26, 2018
- NXP USA, INC.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming inter-level dielectric structures on semiconducto...
- Patent number 9,818,642
- Issue date Nov 14, 2017
- NXP USA, INC.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Applications for nanopillar structures
- Patent number 9,716,141
- Issue date Jul 25, 2017
- NXP USA, INC.
- Mark D. Hall
- B60 - VEHICLES IN GENERAL
Information Patent Grant
Voltage and current limits for electronic device based on temperatu...
- Patent number 9,712,054
- Issue date Jul 18, 2017
- NXP USA, INC.
- Mehul D. Shroff
- G05 - CONTROLLING REGULATING
Information Patent Grant
Semiconductor device with upset event detection and method of making
- Patent number 9,702,925
- Issue date Jul 11, 2017
- NXP USA, INC.
- Mark D. Hall
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fuse/resistor utilizing interconnect and vias and method of making
- Patent number 9,685,405
- Issue date Jun 20, 2017
- NXP USA, INC.
- Mehul D. Shroff
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with graphene encapsulated metal and method th...
- Patent number 9,640,430
- Issue date May 2, 2017
- NXP USA, INC.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D device packaging using through-substrate posts
- Patent number 9,515,006
- Issue date Dec 6, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D device packaging using through-substrate pillars
- Patent number 9,508,701
- Issue date Nov 29, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D device packaging using through-substrate posts
- Patent number 9,508,702
- Issue date Nov 29, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a split-gate device
- Patent number 9,472,418
- Issue date Oct 18, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Mark D. Hall
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Though-substrate vias (TSVs) and method therefor
- Patent number 9,466,569
- Issue date Oct 11, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Mehul D. Shroff
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and method for placing stressors on interconnects within...
- Patent number 9,455,220
- Issue date Sep 27, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Mehul D. Shroff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Capping layer interface interruption for stress migration mitigation
- Patent number 9,443,804
- Issue date Sep 13, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Mehul D. Shroff
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Simulation system and method for testing a simulation of a device a...
- Patent number 9,443,041
- Issue date Sep 13, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Mehul Shroff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Simulation system and method for testing a simulation of a device a...
- Patent number 9,424,379
- Issue date Aug 23, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Xavier Hours
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit heater for reducing stress in the integrated cir...
- Patent number 9,318,409
- Issue date Apr 19, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Implant for performance enhancement of selected transistors in an i...
- Patent number 9,263,441
- Issue date Feb 16, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Mehul D. Shroff
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming a split-gate device
- Patent number 9,252,152
- Issue date Feb 2, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Mark D. Hall
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for electromigration stress mitigation in interconnects...
- Patent number 9,245,086
- Issue date Jan 26, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Ertugrul Demircan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device with embedded heat spreading
- Patent number 9,245,817
- Issue date Jan 26, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Edward O. Travis
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM HAVING SINGLE-EVENT LATCH-UP DETECTION AND MITIGATION
- Publication number 20240364342
- Publication date Oct 31, 2024
- NXP USA, Inc.
- Mohamed Suleman Moosa
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PACKAGED INTEGRATED CIRCUIT HAVING A PHOTODIODE AND A RESISTIVE MEMORY
- Publication number 20210082488
- Publication date Mar 18, 2021
- NXP USA, Inc.
- Nihaar N. Mahatme
- G11 - INFORMATION STORAGE
Information Patent Application
MAGNETIC ATTACK DETECTION IN A MAGNETIC RANDOM ACCESS MEMORY (MRAM)
- Publication number 20200379063
- Publication date Dec 3, 2020
- NXP USA, Inc.
- Nihaar N. Mahatme
- G01 - MEASURING TESTING
Information Patent Application
POST CONTACT AIR GAP FORMATION
- Publication number 20190206740
- Publication date Jul 4, 2019
- NXP USA, Inc.
- Mehul D. SHROFF
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTIGATE TRANSISTOR
- Publication number 20180261682
- Publication date Sep 13, 2018
- NXP USA, Inc.
- Douglas Michael REBER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING INTER-LEVEL DIELECTRIC STRUCTURES ON SEMICONDUCTO...
- Publication number 20180047616
- Publication date Feb 15, 2018
- NXP USA INC.
- DOUGLAS M. REBER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE WITH GRAPHENE ENCAPSULATED METAL AND METHOD TH...
- Publication number 20170194264
- Publication date Jul 6, 2017
- NXP USA, Inc.
- DOUGLAS M. REBER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE WITH GRAPHENE ENCAPSULATED METAL AND METHOD TH...
- Publication number 20170084484
- Publication date Mar 23, 2017
- FREESCALE SEMICONDUCTOR, INC.
- DOUGLAS M. REBER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS AND METHOD FOR PLACING STRESSORS WITHIN AN INTEGRATED CIR...
- Publication number 20170069572
- Publication date Mar 9, 2017
- Freescale Semiconductor, Inc.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOLAR CELL POWERED INTEGRATED CIRCUIT DEVICE AND METHOD THEREFOR
- Publication number 20160343696
- Publication date Nov 24, 2016
- FREESCALE SEMICONDUCTOR, INC.
- DOUGLAS M. REBER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING INTER-LEVEL DIELECTRIC STRUCTURES ON SEMICONDUCTO...
- Publication number 20160307791
- Publication date Oct 20, 2016
- FREESCALE SEMICONDUCTOR, INC.
- DOUGLAS M. REBER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Embedded stress test circuitry and method of operating thereof
- Publication number 20160274180
- Publication date Sep 22, 2016
- FREESCALE SEMICONDUCTOR, INC.
- XAVIER FRANÇOIS MARIE HOURS
- G01 - MEASURING TESTING
Information Patent Application
SAFE OPERATING AREA CHECKING METHOD AND APPARATUS
- Publication number 20160223608
- Publication date Aug 4, 2016
- Xavier HOURS
- G01 - MEASURING TESTING
Information Patent Application
METHOD AND SYSTEM FOR DETERMINING MINIMUM OPERATIONAL VOLTAGE FOR T...
- Publication number 20160171140
- Publication date Jun 16, 2016
- FREESCALE SEMICONDUCTOR, INC.
- SANJAY R. PARIHAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THOUGH-SUBSTRATE VIAS (TSVs) AND METHOD THEREFOR
- Publication number 20160133574
- Publication date May 12, 2016
- FREESCALE SEMICONDUCTOR, INC.
- MEHUL D. SHROFF
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE WITH UPSET EVENT DETECTION AND METHOD OF MAKING
- Publication number 20160109506
- Publication date Apr 21, 2016
- MARK D. HALL
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT HEATER FOR REDUCING STRESS IN THE INTEGRATED CIR...
- Publication number 20160093549
- Publication date Mar 31, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPLICATIONS FOR NANOPILLAR STRUCTURES
- Publication number 20160020278
- Publication date Jan 21, 2016
- FREESCALE SEMICONDUCTOR, INC.
- Mark D. Hall
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
VOLTAGE AND CURRENT LIMITS FOR ELECTRONIC DEVICE BASED ON TEMPERATU...
- Publication number 20150363533
- Publication date Dec 17, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Mehul D. Shroff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR PLACING STRESSORS WITHIN AN INTEGRATED CIR...
- Publication number 20150348898
- Publication date Dec 3, 2015
- FREESCALE SEMICONDUCTOR, INC.
- MEHUL D. SHROFF
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR FORMING A SPLIT-GATE DEVICE
- Publication number 20150279854
- Publication date Oct 1, 2015
- Mark D. Hall
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FORMING A SPLIT-GATE DEVICE
- Publication number 20150279853
- Publication date Oct 1, 2015
- Mark D. Hall
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRESS MIGRATION MITIGATION UTILIZING INDUCED STRESS EFFECTS IN MET...
- Publication number 20150249048
- Publication date Sep 3, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Mehul D. Shroff
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF MAKING A LOGIC TRANSISTOR AND NON-VOLATILE MEMORY (NVM) CELL
- Publication number 20150249140
- Publication date Sep 3, 2015
- MEHUL D. SHROFF
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR CIRCUIT RELIABILITY AGING
- Publication number 20150234961
- Publication date Aug 20, 2015
- Zhichen Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIMULATION SYSTEM AND METHOD FOR TESTING A SIMULATION OF A DEVICE A...
- Publication number 20150143308
- Publication date May 21, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Mehul Shroff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Thin Beam Deposited Fuse
- Publication number 20150137311
- Publication date May 21, 2015
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SIMULATION SYSTEM AND METHOD FOR TESTING A SIMULATION OF A DEVICE A...
- Publication number 20150121325
- Publication date Apr 30, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Xavier Hours
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D DEVICE PACKAGING USING THROUGH-SUBSTRATE PILLARS
- Publication number 20150091178
- Publication date Apr 2, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
3D DEVICE PACKAGING USING THROUGH-SUBSTRATE POSTS
- Publication number 20150091187
- Publication date Apr 2, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Douglas M. Reber
- H01 - BASIC ELECTRIC ELEMENTS

Mehul D. Shroff

Person

Patents Grantslast 30 patents

Packaged integrated circuit having a photodiode and a resistive memory

Magnetic attack detection in a magnetic random access memory (MRAM)

Post contact air gap formation

Method of forming inter-level dielectric structures on semiconducto...

Semiconductor device with graphene encapsulated metal and method th...

Multigate transistor

Safe operating area checking method and apparatus

Substrate contacts for a transistor

Apparatus and method for placing stressors within an integrated cir...

Solar cell powered integrated circuit device and method therefor

Method of forming inter-level dielectric structures on semiconducto...

Applications for nanopillar structures

Voltage and current limits for electronic device based on temperatu...

Semiconductor device with upset event detection and method of making

Fuse/resistor utilizing interconnect and vias and method of making

Semiconductor device with graphene encapsulated metal and method th...

3D device packaging using through-substrate posts

3D device packaging using through-substrate pillars

3D device packaging using through-substrate posts

Method for forming a split-gate device

Though-substrate vias (TSVs) and method therefor

Apparatus and method for placing stressors on interconnects within...

Capping layer interface interruption for stress migration mitigation

Simulation system and method for testing a simulation of a device a...

Simulation system and method for testing a simulation of a device a...

Integrated circuit heater for reducing stress in the integrated cir...

Implant for performance enhancement of selected transistors in an i...

Method for forming a split-gate device

Techniques for electromigration stress mitigation in interconnects...

Semiconductor device with embedded heat spreading

Patents Applicationslast 30 patents

SYSTEM HAVING SINGLE-EVENT LATCH-UP DETECTION AND MITIGATION

PACKAGED INTEGRATED CIRCUIT HAVING A PHOTODIODE AND A RESISTIVE MEMORY

MAGNETIC ATTACK DETECTION IN A MAGNETIC RANDOM ACCESS MEMORY (MRAM)

POST CONTACT AIR GAP FORMATION

MULTIGATE TRANSISTOR

METHOD OF FORMING INTER-LEVEL DIELECTRIC STRUCTURES ON SEMICONDUCTO...

SEMICONDUCTOR DEVICE WITH GRAPHENE ENCAPSULATED METAL AND METHOD TH...

SEMICONDUCTOR DEVICE WITH GRAPHENE ENCAPSULATED METAL AND METHOD TH...

APPARATUS AND METHOD FOR PLACING STRESSORS WITHIN AN INTEGRATED CIR...

SOLAR CELL POWERED INTEGRATED CIRCUIT DEVICE AND METHOD THEREFOR

METHOD OF FORMING INTER-LEVEL DIELECTRIC STRUCTURES ON SEMICONDUCTO...

Embedded stress test circuitry and method of operating thereof

SAFE OPERATING AREA CHECKING METHOD AND APPARATUS

METHOD AND SYSTEM FOR DETERMINING MINIMUM OPERATIONAL VOLTAGE FOR T...

THOUGH-SUBSTRATE VIAS (TSVs) AND METHOD THEREFOR

SEMICONDUCTOR DEVICE WITH UPSET EVENT DETECTION AND METHOD OF MAKING

INTEGRATED CIRCUIT HEATER FOR REDUCING STRESS IN THE INTEGRATED CIR...

APPLICATIONS FOR NANOPILLAR STRUCTURES

VOLTAGE AND CURRENT LIMITS FOR ELECTRONIC DEVICE BASED ON TEMPERATU...

APPARATUS AND METHOD FOR PLACING STRESSORS WITHIN AN INTEGRATED CIR...

METHOD FOR FORMING A SPLIT-GATE DEVICE

METHOD FOR FORMING A SPLIT-GATE DEVICE

STRESS MIGRATION MITIGATION UTILIZING INDUCED STRESS EFFECTS IN MET...

METHOD OF MAKING A LOGIC TRANSISTOR AND NON-VOLATILE MEMORY (NVM) CELL

METHOD AND APPARATUS FOR CIRCUIT RELIABILITY AGING

SIMULATION SYSTEM AND METHOD FOR TESTING A SIMULATION OF A DEVICE A...

Thin Beam Deposited Fuse

SIMULATION SYSTEM AND METHOD FOR TESTING A SIMULATION OF A DEVICE A...

3D DEVICE PACKAGING USING THROUGH-SUBSTRATE PILLARS

3D DEVICE PACKAGING USING THROUGH-SUBSTRATE POSTS