Mei-Sheng Zhou

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus to reduce thermal variations within an integra...
- Patent number 8,860,142
- Issue date Oct 14, 2014
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Debora Chyiu Hyia Poon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strained channel transistor structure and method
- Patent number 8,754,447
- Issue date Jun 17, 2014
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Jin Ping Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a semiconductor device having an epitaxial c...
- Patent number 8,716,076
- Issue date May 6, 2014
- GlobalFoundries Singapore Pte. Ltd.
- Jinping Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit and method of fabrication thereof
- Patent number 8,546,873
- Issue date Oct 1, 2013
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Jinping Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for reducing loading effects during film formation
- Patent number 8,415,236
- Issue date Apr 9, 2013
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Han Guan Chew
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Processing with reduced line end shortening ratio
- Patent number 8,394,724
- Issue date Mar 12, 2013
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Hai Cong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming high-k dielectric stop layer for contact hole ope...
- Patent number 8,354,347
- Issue date Jan 15, 2013
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Jianhui Ye
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Implementation of temperature-dependent phase switch layer for impr...
- Patent number 8,324,011
- Issue date Dec 4, 2012
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Chyiu Hyia Poon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus to reduce thermal variations within an integra...
- Patent number 8,293,544
- Issue date Oct 23, 2012
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Debora Chyiu Hyia Poon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit and method of fabrication thereof
- Patent number 8,058,123
- Issue date Nov 15, 2011
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Jinping Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for fabricating a semiconductor device having an epitaxial c...
- Patent number 8,012,839
- Issue date Sep 6, 2011
- Chartered Semiconductor Manufacturing, Ltd.
- Jinping Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-variable regression for metrology
- Patent number 7,966,142
- Issue date Jun 21, 2011
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Wen Zhan Zhou
- G01 - MEASURING TESTING
Information Patent Grant
Method for reducing silicide defects in integrated circuits
- Patent number 7,960,283
- Issue date Jun 14, 2011
- Chartered Semiconductor Manufacturing, Ltd.
- Jeff Jianhui Ye
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Damascene contact structure for integrated circuits
- Patent number 7,902,066
- Issue date Mar 8, 2011
- Chartered Semiconductor Manufacturing, Ltd.
- Jian Hui Ye
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thin film etching method and semiconductor device fabrication using...
- Patent number 7,879,732
- Issue date Feb 1, 2011
- Chartered Semiconductor Manufacturing Ltd.
- Xiang Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strained channel transistor structure and method
- Patent number 7,776,699
- Issue date Aug 17, 2010
- Chartered Semiconductor Manufacturing, Ltd.
- Jin Ping Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for reducing silicide defects in integrated circuits
- Patent number 7,745,320
- Issue date Jun 29, 2010
- Chartered Semiconductor Manufacturing, Ltd.
- Jeff Jianhui Ye
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of copper/copper surface bonding using a conducting polymer...
- Patent number 7,452,808
- Issue date Nov 18, 2008
- Chartered Semiconductor Manufacturing Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Surface modification of a porous organic material through the use o...
- Patent number 7,354,623
- Issue date Apr 8, 2008
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ching-Ya Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Micro-etching method to replicate alignment marks for semiconductor...
- Patent number 7,338,909
- Issue date Mar 4, 2008
- Taiwan Semiconductor Manufacturing Co. Ltd.
- Yu-Liang Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Poly(arylene ether) dielectrics
- Patent number 7,179,879
- Issue date Feb 20, 2007
- Chartered Semiconductor Manufacturing Ltd.
- Christopher Lim
- C08 - ORGANIC MACROMOLECULAR COMPOUNDS THEIR PREPARATION OR CHEMICAL WORKING-...
Information Patent Grant
Poly(arylene ether) dielectrics
- Patent number 7,166,250
- Issue date Jan 23, 2007
- Chartered Semiconductor Manufacturing Ltd.
- Christopher Lim
- C08 - ORGANIC MACROMOLECULAR COMPOUNDS THEIR PREPARATION OR CHEMICAL WORKING-...
Information Patent Grant
Planarizing method employing hydrogenated silicon nitride planarizi...
- Patent number 7,129,151
- Issue date Oct 31, 2006
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ping Chuang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Advanced process control approach for Cu interconnect wiring sheet...
- Patent number 7,083,495
- Issue date Aug 1, 2006
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chun Hsien Lin
- B24 - GRINDING POLISHING
Information Patent Grant
Poly(arylene ether) dielectrics
- Patent number 7,071,281
- Issue date Jul 4, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Christopher Lim
- C08 - ORGANIC MACROMOLECULAR COMPOUNDS THEIR PREPARATION OR CHEMICAL WORKING-...
Information Patent Grant
Method of copper/copper surface bonding using a conducting polymer...
- Patent number 7,060,613
- Issue date Jun 13, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual metal gate process: metals and their silicides
- Patent number 7,005,716
- Issue date Feb 28, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Wenhe Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Copper diffusion deterrent interface
- Patent number 6,987,321
- Issue date Jan 17, 2006
- Chartered Semiconductor Manufacturing Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of copper/copper surface bonding using a conducting polymer...
- Patent number 6,967,162
- Issue date Nov 22, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Simon Chooi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods to form dual metal gates by incorporating metals and their...
- Patent number 6,891,233
- Issue date May 10, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Wenhe Lin
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND APPARATUS TO REDUCE THERMAL VARIATIONS WITHIN AN INTEGRA...
- Publication number 20130099321
- Publication date Apr 25, 2013
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Debora Chyiu Hyia Poon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT AND METHOD OF FABRICATION THEREOF
- Publication number 20120012940
- Publication date Jan 19, 2012
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Jinping LIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING AN EPITAXIAL C...
- Publication number 20110281410
- Publication date Nov 17, 2011
- Chartered Semiconductor Manufacturing Ltd.
- JINPING LIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRAINED CHANNEL TRANSISTOR STRUCTURE AND METHOD
- Publication number 20100308374
- Publication date Dec 9, 2010
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Jin Ping LIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR REDUCING SILICIDE DEFECTS IN INTEGRATED CIRCUITS
- Publication number 20100267236
- Publication date Oct 21, 2010
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Jianhui YE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR REDUCING LOADING EFFECTS DURING FILM FORMATION
- Publication number 20100167505
- Publication date Jul 1, 2010
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Han Guan CHEW
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH STRESS FILM
- Publication number 20100096695
- Publication date Apr 22, 2010
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Han Guan Chew
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and apparatus to reduce thermal variations within an integra...
- Publication number 20100019329
- Publication date Jan 28, 2010
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Debora Chyiu Hyia Poon
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR REDUCING SILICIDE DEFECTS IN INTEGRATED CIRCUITS
- Publication number 20090289309
- Publication date Nov 26, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Jianhui YE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High shrinkage stress silicon nitride (SiN) layer for NFET improvement
- Publication number 20090289284
- Publication date Nov 26, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Luona Goh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-VARIABLE REGRESSION FOR METROLOGY
- Publication number 20090258445
- Publication date Oct 15, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Wen Zhan ZHOU
- G01 - MEASURING TESTING
Information Patent Application
METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING AN EPITAXIAL C...
- Publication number 20090218597
- Publication date Sep 3, 2009
- Jinping Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRAINED CHANNEL TRANSISTOR STRUCTURE AND METHOD
- Publication number 20090194788
- Publication date Aug 6, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Jin Ping LIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THIN FILM ETCHING METHOD AND SEMICONDUCTOR DEVICE FABRICATION USING...
- Publication number 20090156010
- Publication date Jun 18, 2009
- Xiang Hu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming high-k dielectric stop layer for contact hole ope...
- Publication number 20090146296
- Publication date Jun 11, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Jianhui YE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT AND METHOD OF FABRICATION THEREOF
- Publication number 20090140292
- Publication date Jun 4, 2009
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Jinping LIU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IMPLEMENTATION OF TEMPERATURE-DEPENDENT PHASE SWITCH LAYER FOR IMPR...
- Publication number 20090068825
- Publication date Mar 12, 2009
- CHYIU HYIA POON
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE HAVING HETEROGENEO...
- Publication number 20090053864
- Publication date Feb 26, 2009
- Jinping Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Damascene Contact Structure for Integrated Circuits
- Publication number 20080076244
- Publication date Mar 27, 2008
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Jian Hui YE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Processing with Reduced Line End Shortening Ratio
- Publication number 20080054477
- Publication date Mar 6, 2008
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Hai CONG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-ZONE CARRIER HEAD FOR CHEMICAL MECHANICAL POLISHING AND CMP M...
- Publication number 20070167110
- Publication date Jul 19, 2007
- Yu-Hsiang Tseng
- B24 - GRINDING POLISHING
Information Patent Application
Continuous liquid delivery system with anti-clog function
- Publication number 20060043029
- Publication date Mar 2, 2006
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Chih-Tien Chang
- B01 - PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
Information Patent Application
Micro-etching method to replicate alignment marks for semiconductor...
- Publication number 20050282396
- Publication date Dec 22, 2005
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yu-Liang Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Surface modification of a porous organic material through the use o...
- Publication number 20050260402
- Publication date Nov 24, 2005
- Ching-Ya Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Chemical agent additives in copper CMP slurry
- Publication number 20050205522
- Publication date Sep 22, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Paul Kwok Keung Ho
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
FIB exposure of alignment marks in MIM technology
- Publication number 20050186753
- Publication date Aug 25, 2005
- Ping-Hsu Chen
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Novel poly(arylene ether) dielectrics
- Publication number 20050159576
- Publication date Jul 21, 2005
- Chartered Semiconductor Manufacturing Ltd.
- Christopher Lim
- C08 - ORGANIC MACROMOLECULAR COMPOUNDS THEIR PREPARATION OR CHEMICAL WORKING-...
Information Patent Application
Method of integrating post-etching cleaning process with deposition...
- Publication number 20050158664
- Publication date Jul 21, 2005
- Joshua Tseng
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Rapid temperature compensation module for semiconductor tool
- Publication number 20050145614
- Publication date Jul 7, 2005
- Taiwan Semiconductor Manufacturing Co., LTD
- Hsueh-Chang Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming an oxide layer using a mixture of a supercritical...
- Publication number 20050130449
- Publication date Jun 16, 2005
- Ping Chuang
- B01 - PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL

Mei-Sheng Zhou

Person

Patents Grantslast 30 patents

Method and apparatus to reduce thermal variations within an integra...

Strained channel transistor structure and method

Method for fabricating a semiconductor device having an epitaxial c...

Integrated circuit and method of fabrication thereof

Methods for reducing loading effects during film formation

Processing with reduced line end shortening ratio

Method of forming high-k dielectric stop layer for contact hole ope...

Implementation of temperature-dependent phase switch layer for impr...

Method and apparatus to reduce thermal variations within an integra...

Integrated circuit and method of fabrication thereof

Method for fabricating a semiconductor device having an epitaxial c...

Multi-variable regression for metrology

Method for reducing silicide defects in integrated circuits

Damascene contact structure for integrated circuits

Thin film etching method and semiconductor device fabrication using...

Strained channel transistor structure and method

Method for reducing silicide defects in integrated circuits

Method of copper/copper surface bonding using a conducting polymer...

Surface modification of a porous organic material through the use o...

Micro-etching method to replicate alignment marks for semiconductor...

Poly(arylene ether) dielectrics

Poly(arylene ether) dielectrics

Planarizing method employing hydrogenated silicon nitride planarizi...

Advanced process control approach for Cu interconnect wiring sheet...

Poly(arylene ether) dielectrics

Method of copper/copper surface bonding using a conducting polymer...

Dual metal gate process: metals and their silicides

Copper diffusion deterrent interface

Method of copper/copper surface bonding using a conducting polymer...

Methods to form dual metal gates by incorporating metals and their...

Patents Applicationslast 30 patents

METHOD AND APPARATUS TO REDUCE THERMAL VARIATIONS WITHIN AN INTEGRA...

INTEGRATED CIRCUIT AND METHOD OF FABRICATION THEREOF

METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING AN EPITAXIAL C...

STRAINED CHANNEL TRANSISTOR STRUCTURE AND METHOD

METHOD FOR REDUCING SILICIDE DEFECTS IN INTEGRATED CIRCUITS

METHODS FOR REDUCING LOADING EFFECTS DURING FILM FORMATION

HIGH STRESS FILM

Method and apparatus to reduce thermal variations within an integra...

METHOD FOR REDUCING SILICIDE DEFECTS IN INTEGRATED CIRCUITS

High shrinkage stress silicon nitride (SiN) layer for NFET improvement

MULTI-VARIABLE REGRESSION FOR METROLOGY

METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING AN EPITAXIAL C...

STRAINED CHANNEL TRANSISTOR STRUCTURE AND METHOD

THIN FILM ETCHING METHOD AND SEMICONDUCTOR DEVICE FABRICATION USING...

Method of forming high-k dielectric stop layer for contact hole ope...

INTEGRATED CIRCUIT AND METHOD OF FABRICATION THEREOF

IMPLEMENTATION OF TEMPERATURE-DEPENDENT PHASE SWITCH LAYER FOR IMPR...

METHOD FOR FABRICATING A SEMICONDUCTOR STRUCTURE HAVING HETEROGENEO...

Damascene Contact Structure for Integrated Circuits

Processing with Reduced Line End Shortening Ratio

MULTI-ZONE CARRIER HEAD FOR CHEMICAL MECHANICAL POLISHING AND CMP M...

Continuous liquid delivery system with anti-clog function

Micro-etching method to replicate alignment marks for semiconductor...

Surface modification of a porous organic material through the use o...

Chemical agent additives in copper CMP slurry

FIB exposure of alignment marks in MIM technology

Novel poly(arylene ether) dielectrics

Method of integrating post-etching cleaning process with deposition...

Rapid temperature compensation module for semiconductor tool

Method of forming an oxide layer using a mixture of a supercritical...