Michael C. Parris

Person

Colorado Springs, CO, US

People

Patents Grantslast 30 patents

Information Patent Grant
System and method for testing fuse blow reliability for integrated...
- Patent number 9,557,364
- Issue date Jan 31, 2017
- Tessera, Inc.
- Michael Curtis Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
DRAM security erase
- Patent number 9,558,808
- Issue date Jan 31, 2017
- Tessera, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
DRAM security erase
- Patent number 9,299,417
- Issue date Mar 29, 2016
- Tessera, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory devices having vertical drain to gate capacitiv...
- Patent number 9,230,814
- Issue date Jan 5, 2016
- Invensas Corporation
- David Edward Fisch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power boosting circuit for semiconductor packaging
- Patent number 9,158,352
- Issue date Oct 13, 2015
- Tessera, Inc.
- Richard Dewitt Crisp
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DRAM security erase
- Patent number 8,976,572
- Issue date Mar 10, 2015
- Tessera, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Embedded passive integration
- Patent number 8,970,003
- Issue date Mar 3, 2015
- Tessera, Inc.
- Michael Curtis Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Common doped region with separate gate control for a logic compatib...
- Patent number 8,873,302
- Issue date Oct 28, 2014
- Invensas Corporation
- David Edward Fisch
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for testing fuse blow reliability for integrated...
- Patent number 8,736,278
- Issue date May 27, 2014
- Tessera Inc.
- Michael Curtis Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
DRAM security erase
- Patent number 8,699,263
- Issue date Apr 15, 2014
- Tessera, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Power boosting circuit for semiconductor packaging
- Patent number 8,692,611
- Issue date Apr 8, 2014
- Tessera, Inc.
- Richard Dewitt Crisp
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data inversion register technique for integrated circuit memory tes...
- Patent number RE44726
- Issue date Jan 21, 2014
- Invensas Corporation
- Michael C. Parris
- 714 - Error detection/correction and fault detection/recovery
Information Patent Grant
Dual bit line precharge architecture and method for low power dynam...
- Patent number 8,339,882
- Issue date Dec 25, 2012
- ProMOS Technologies Pte. Ltd.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Error correction code (ECC) circuit test mode
- Patent number 8,281,219
- Issue date Oct 2, 2012
- Invensas Corporation
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Twin cell architecture for integrated circuit dynamic random access...
- Patent number 7,916,567
- Issue date Mar 29, 2011
- ProMOS Technologies Pte. Ltd.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Short-circuit charge-sharing technique for integrated circuit devices
- Patent number 7,649,406
- Issue date Jan 19, 2010
- United Memories, Inc.
- Michael C. Parris
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Data inversion register technique for integrated circuit memory tes...
- Patent number 7,631,233
- Issue date Dec 8, 2009
- United Memories, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Switched capacitor charge sharing technique for integrated circuit...
- Patent number 7,609,570
- Issue date Oct 27, 2009
- United Memories, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Optimized charge sharing for data bus skew applications
- Patent number 7,606,093
- Issue date Oct 20, 2009
- United Memories, Inc.
- Michael C. Parris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low skew clock distribution tree
- Patent number 7,586,355
- Issue date Sep 8, 2009
- United Memories, Inc.
- Michael C. Parris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiple bus charge sharing
- Patent number 7,580,304
- Issue date Aug 25, 2009
- United Memories, Inc.
- Michael C. Parris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Static random access memory (SRAM) compatible, high availability me...
- Patent number 7,506,100
- Issue date Mar 17, 2009
- United Memories, Inc.
- Douglas Blaine Butler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data bus charge-sharing technique for integrated circuit devices
- Patent number 7,463,054
- Issue date Dec 9, 2008
- United Memories, Inc.
- Michael C. Parris
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Layout area efficient, high speed, dynamic multi-input exclusive or...
- Patent number 7,298,171
- Issue date Nov 20, 2007
- United Memories, Inc.
- Michael C. Parris
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Powergating method and apparatus
- Patent number 7,180,363
- Issue date Feb 20, 2007
- United Memories, Inc.
- Michael C. Parris
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reduced gate delay multiplexed interface and output buffer circuit...
- Patent number 7,161,214
- Issue date Jan 9, 2007
- United Memories, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock signal initiated precharge technique for active memory subarr...
- Patent number 7,154,795
- Issue date Dec 26, 2006
- United Memories, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual access DRAM
- Patent number 7,110,306
- Issue date Sep 19, 2006
- United Memories, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power sleep mode operation technique for dynamic random access...
- Patent number 7,099,234
- Issue date Aug 29, 2006
- United Memories, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Grant
Powergate control using boosted and negative voltages
- Patent number 7,053,692
- Issue date May 30, 2006
- United Memories, Inc.
- Michael C. Parris
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
DRAM security erase
- Publication number 20160211009
- Publication date Jul 21, 2016
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Application
DRAM SECURITY ERASE
- Publication number 20150287452
- Publication date Oct 8, 2015
- Tessera, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Application
POWER BOOSTING CIRCUIT FOR SEMICONDUCTOR PACKAGING
- Publication number 20140333371
- Publication date Nov 13, 2014
- Tessera, Inc.
- Richard Dewitt Crisp
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR TESTING FUSE BLOW RELIABILITY FOR INTEGRATED...
- Publication number 20140253145
- Publication date Sep 11, 2014
- Tessera, Inc.
- Michael Curtis Parris
- G01 - MEASURING TESTING
Information Patent Application
DRAM SECURITY ERASE
- Publication number 20140185402
- Publication date Jul 3, 2014
- Tessera, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY DEVICES HAVING VERTICAL DRAIN TO GATE CAPACITIV...
- Publication number 20130107630
- Publication date May 2, 2013
- Invensas Corporation
- David Edward Fisch
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMMON DOPED REGION WITH SEPARATE GATE CONTROL FOR A LOGIC COMPATIB...
- Publication number 20130107635
- Publication date May 2, 2013
- Invensas Corporation
- David Edward Fisch
- G11 - INFORMATION STORAGE
Information Patent Application
DRAM SECURITY ERASE
- Publication number 20130051127
- Publication date Feb 28, 2013
- Tessera, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Application
POWER BOOSTING CIRCUIT FOR SEMICONDUCTOR PACKAGING
- Publication number 20130043935
- Publication date Feb 21, 2013
- Tessera, Inc.
- Richard Dewitt Crisp
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EMBEDDED PASSIVE INTEGRATION
- Publication number 20130027899
- Publication date Jan 31, 2013
- Tessera, Inc.
- Michael Curtis Parris
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND METHOD FOR TESTING FUSE BLOW RELIABILITY FOR INTEGRATED...
- Publication number 20130027056
- Publication date Jan 31, 2013
- Tessera. Inc.
- Michael Curtis Parris
- G01 - MEASURING TESTING
Information Patent Application
DUAL BIT LINE PRECHARGE ARCHITECTURE AND METHOD FOR LOW POWER DYNAM...
- Publication number 20120008445
- Publication date Jan 12, 2012
- ProMOS Technologies PTE.LTD.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL BIT LINE PRECHARGE ARCHITECTURE AND METHOD FOR LOW POWER DYNAM...
- Publication number 20120008444
- Publication date Jan 12, 2012
- ProMOS Technologies PTE.LTD.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Application
TWIN CELL ARCHITECTURE FOR INTEGRATED CIRCUIT DYNAMIC RANDOM ACCESS...
- Publication number 20090225613
- Publication date Sep 10, 2009
- PROMOS TECHNOLOGIES PTE.LTD.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Application
STATIC RANDOM ACCESS MEMORY (SRAM) COMPATIBLE, HIGH AVAILABILITY ME...
- Publication number 20090106488
- Publication date Apr 23, 2009
- United Memories, Inc.
- Douglas Blaine Butler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA INVERSION REGISTER TECHNIQUE FOR INTEGRATED CIRCUIT MEMORY TES...
- Publication number 20090094497
- Publication date Apr 9, 2009
- United Memories, Inc.
- Michael C. Parris
- G01 - MEASURING TESTING
Information Patent Application
EARLY WRITE WITH DATA MASKING TECHNIQUE FOR INTEGRATED CIRCUIT DYNA...
- Publication number 20090073786
- Publication date Mar 19, 2009
- United Memories, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Application
SHORT-CIRCUIT CHARGE-SHARING TECHNIQUE FOR INTEGRATED CIRCUIT DEVICES
- Publication number 20090072879
- Publication date Mar 19, 2009
- United Memories, Inc.
- Michael C. Parris
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ERROR CORRECTION CODE (ECC) CIRCUIT TEST MODE
- Publication number 20090049350
- Publication date Feb 19, 2009
- United Memories, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Application
LOW SKEW CLOCK DISTRIBUTION TREE
- Publication number 20090015311
- Publication date Jan 15, 2009
- United Memories, Inc.
- Michael C. Parris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE BUS CHARGE SHARING
- Publication number 20080313379
- Publication date Dec 18, 2008
- United Memories, Inc.
- Michael C. Parris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZED CHARGE SHARING FOR DATA BUS SKEW APPLICATIONS
- Publication number 20080174340
- Publication date Jul 24, 2008
- United Memories, Inc.
- Michael C. Parris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SWITCHED CAPACITOR CHARGE SHARING TECHNIQUE FOR INTEGRATED CIRCUIT...
- Publication number 20080175074
- Publication date Jul 24, 2008
- United Memories, Inc.
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Application
Layout area efficient, high speed, dynamic multi-input exclusive or...
- Publication number 20070008014
- Publication date Jan 11, 2007
- United Memories, Inc.
- Michael C. Parris
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Static random access memory (SRAM) compatible, high availability me...
- Publication number 20060190678
- Publication date Aug 24, 2006
- Douglas Blaine Butler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Static random access memory (SRAM) compatible, high availability me...
- Publication number 20060190676
- Publication date Aug 24, 2006
- United Memories, Inc. Colorado Springs
- Douglas Blaine Butler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Powergating method and apparatus
- Publication number 20060022742
- Publication date Feb 2, 2006
- Michael C. Parris
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clock signal initiated precharge technique for active memory subarr...
- Publication number 20060023530
- Publication date Feb 2, 2006
- Michael C. Parris
- G11 - INFORMATION STORAGE
Information Patent Application
Cache and tag power-down function during low-power data retention s...
- Publication number 20060005053
- Publication date Jan 5, 2006
- Oscar Frederick Jones
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dual-port DRAM cell with simultaneous access
- Publication number 20050289293
- Publication date Dec 29, 2005
- Michael C. Parris
- G11 - INFORMATION STORAGE

Michael C. Parris

Person

Patents Grantslast 30 patents

System and method for testing fuse blow reliability for integrated...

DRAM security erase

DRAM security erase

Non-volatile memory devices having vertical drain to gate capacitiv...

Power boosting circuit for semiconductor packaging

DRAM security erase

Embedded passive integration

Common doped region with separate gate control for a logic compatib...

System and method for testing fuse blow reliability for integrated...

DRAM security erase

Power boosting circuit for semiconductor packaging

Data inversion register technique for integrated circuit memory tes...

Dual bit line precharge architecture and method for low power dynam...

Error correction code (ECC) circuit test mode

Twin cell architecture for integrated circuit dynamic random access...

Short-circuit charge-sharing technique for integrated circuit devices

Data inversion register technique for integrated circuit memory tes...

Switched capacitor charge sharing technique for integrated circuit...

Optimized charge sharing for data bus skew applications

Low skew clock distribution tree

Multiple bus charge sharing

Static random access memory (SRAM) compatible, high availability me...

Data bus charge-sharing technique for integrated circuit devices

Layout area efficient, high speed, dynamic multi-input exclusive or...

Powergating method and apparatus

Reduced gate delay multiplexed interface and output buffer circuit...

Clock signal initiated precharge technique for active memory subarr...

Dual access DRAM

Low power sleep mode operation technique for dynamic random access...

Powergate control using boosted and negative voltages

Patents Applicationslast 30 patents

DRAM security erase

DRAM SECURITY ERASE

POWER BOOSTING CIRCUIT FOR SEMICONDUCTOR PACKAGING

SYSTEM AND METHOD FOR TESTING FUSE BLOW RELIABILITY FOR INTEGRATED...

DRAM SECURITY ERASE

NON-VOLATILE MEMORY DEVICES HAVING VERTICAL DRAIN TO GATE CAPACITIV...

COMMON DOPED REGION WITH SEPARATE GATE CONTROL FOR A LOGIC COMPATIB...

DRAM SECURITY ERASE

POWER BOOSTING CIRCUIT FOR SEMICONDUCTOR PACKAGING

EMBEDDED PASSIVE INTEGRATION

SYSTEM AND METHOD FOR TESTING FUSE BLOW RELIABILITY FOR INTEGRATED...

DUAL BIT LINE PRECHARGE ARCHITECTURE AND METHOD FOR LOW POWER DYNAM...

DUAL BIT LINE PRECHARGE ARCHITECTURE AND METHOD FOR LOW POWER DYNAM...

TWIN CELL ARCHITECTURE FOR INTEGRATED CIRCUIT DYNAMIC RANDOM ACCESS...

STATIC RANDOM ACCESS MEMORY (SRAM) COMPATIBLE, HIGH AVAILABILITY ME...

DATA INVERSION REGISTER TECHNIQUE FOR INTEGRATED CIRCUIT MEMORY TES...

EARLY WRITE WITH DATA MASKING TECHNIQUE FOR INTEGRATED CIRCUIT DYNA...

SHORT-CIRCUIT CHARGE-SHARING TECHNIQUE FOR INTEGRATED CIRCUIT DEVICES

ERROR CORRECTION CODE (ECC) CIRCUIT TEST MODE

LOW SKEW CLOCK DISTRIBUTION TREE

MULTIPLE BUS CHARGE SHARING

OPTIMIZED CHARGE SHARING FOR DATA BUS SKEW APPLICATIONS

SWITCHED CAPACITOR CHARGE SHARING TECHNIQUE FOR INTEGRATED CIRCUIT...

Layout area efficient, high speed, dynamic multi-input exclusive or...

Static random access memory (SRAM) compatible, high availability me...

Static random access memory (SRAM) compatible, high availability me...

Powergating method and apparatus

Clock signal initiated precharge technique for active memory subarr...

Cache and tag power-down function during low-power data retention s...

Dual-port DRAM cell with simultaneous access