Michael J. McManus

Person

Liberty Township, OH, US

People

Patents Grantslast 30 patents

Information Patent Grant
Uniform-footprint programmable-skew multi-stage CMOS cell
- Patent number 8,779,820
- Issue date Jul 15, 2014
- LSI Corporation
- Martin J. Gasper
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Uniform-footprint programmable-skew multi-stage delay cell
- Patent number 8,664,995
- Issue date Mar 4, 2014
- LSI Corporation
- Martin J. Gasper
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Uniform-footprint programmable-skew multi-stage delay cell
- Patent number 8,536,921
- Issue date Sep 17, 2013
- LSI Corporation
- Martin J. Gasper
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for integrated circuit design with library cells
- Patent number 7,051,308
- Issue date May 23, 2006
- Virtual Silicon Technology, Inc.
- Michael J. McManus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuitry to provide a low power input buffer
- Patent number 6,844,770
- Issue date Jan 18, 2005
- Virtual Silicon Technology, Inc.
- Michael J. McManus
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for design of integrated circuits
- Patent number 6,839,882
- Issue date Jan 4, 2005
- Virtual Silicon Technology, Inc.
- Michael J. McManus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for integrated circuit design with a software...
- Patent number 6,766,496
- Issue date Jul 20, 2004
- Virtual Silicon Technology, Inc.
- Michael J. McManus
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Uniform-Footprint Programmable-Skew Multi-Stage Delay Cell
- Publication number 20140082577
- Publication date Mar 20, 2014
- LSI Corporation
- Martin J. Gasper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UNIFORM-FOOTPRINT PROGRAMMABLE-SKEW MULTI-STAGE DELAY CELL
- Publication number 20130321054
- Publication date Dec 5, 2013
- LSI Corporation
- Martin J. Gasper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UNIFORM-FOOTPRINT PROGRAMMABLE-SKEW MULTI-STAGE DELAY CELL
- Publication number 20130069703
- Publication date Mar 21, 2013
- LSI CORPORATION
- Martin J. Gasper
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Circuitry to provide a low power input buffer
- Publication number 20040021509
- Publication date Feb 5, 2004
- Virtual Silicon Technologies, Inc., a Delaware corporation
- Michael J. McManus
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and apparatus for design of integrated circuits
- Publication number 20030023937
- Publication date Jan 30, 2003
- Michael J. McManus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for integrated circuit design with library cells
- Publication number 20030023935
- Publication date Jan 30, 2003
- Michael J. McManus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for integrated circuit design with a software...
- Publication number 20030023936
- Publication date Jan 30, 2003
- Michael J. McManus
- G06 - COMPUTING CALCULATING COUNTING

Michael J. McManus

Person

Patents Grantslast 30 patents

Uniform-footprint programmable-skew multi-stage CMOS cell

Uniform-footprint programmable-skew multi-stage delay cell

Uniform-footprint programmable-skew multi-stage delay cell

Method and apparatus for integrated circuit design with library cells

Circuitry to provide a low power input buffer

Method and apparatus for design of integrated circuits

Method and apparatus for integrated circuit design with a software...

Patents Applicationslast 30 patents

Uniform-Footprint Programmable-Skew Multi-Stage Delay Cell

UNIFORM-FOOTPRINT PROGRAMMABLE-SKEW MULTI-STAGE DELAY CELL

UNIFORM-FOOTPRINT PROGRAMMABLE-SKEW MULTI-STAGE DELAY CELL

Circuitry to provide a low power input buffer

Method and apparatus for design of integrated circuits

Method and apparatus for integrated circuit design with library cells

Method and apparatus for integrated circuit design with a software...