Michihiro Yamada

Person

Hyogo, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor memory device and method of data transfer therefor
- Patent number 5,481,496
- Issue date Jan 2, 1996
- Mitsubishi Denki Kabushiki Kaisha
- Toshifumi Kobayashi
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device having multiple memory arrays and inclu...
- Patent number 5,323,348
- Issue date Jun 21, 1994
- Mitsubishi Denki Kabushiki Kaisha
- Shigeru Mori
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device and method of testing the same
- Patent number 5,305,261
- Issue date Apr 19, 1994
- Mitsubishi Denki Kabushiki Kaisha
- Kiyohiro Furutani
- G11 - INFORMATION STORAGE
Information Patent Grant
Input circuit of a semiconductor device
- Patent number 5,208,474
- Issue date May 4, 1993
- Mitsubishi Denki Kabushiki Denki
- Tadato Yamagata
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fibricating a semiconductor device having a trench
- Patent number 5,112,771
- Issue date May 12, 1992
- Mitsubishi Denki Kabushiki Kaisha
- Tatsuya Ishii
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of and apparatus for reducing current of semiconductor memor...
- Patent number 5,073,874
- Issue date Dec 17, 1991
- Mitsubishi Denki Kabushiki Kaisha
- Michihiro Yamada
- G11 - INFORMATION STORAGE
Information Patent Grant
Delay circuit employing different threshold FET's
- Patent number 5,063,313
- Issue date Nov 5, 1991
- Mitsubishi Denki Kabushiki Kaisha
- Shigeru Kikuda
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic random access memory with FET equalization of bit lines
- Patent number 5,053,997
- Issue date Oct 1, 1991
- Mitsubishi Denki Kabushiki Kaisha
- Hiroshi Miyamato
- G11 - INFORMATION STORAGE
Information Patent Grant
Input protective apparatus of semiconductor device
- Patent number 5,019,883
- Issue date May 28, 1991
- Mitsubishi Denki Kabushiki Kaisha
- Shigeru Mori
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Electric fuse for a redundancy circuit
- Patent number 4,984,054
- Issue date Jan 8, 1991
- Mitsubishi Denki Kabushiki Kaisha
- Michihiro Yamada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Arbiter circuit for processing concurrent requests for access to sh...
- Patent number 4,962,379
- Issue date Oct 9, 1990
- Mitsubishi Denki Kabushiki Kaisha
- Kenichi Yasuda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of and apparatus for reducing current of semiconductor memor...
- Patent number 4,933,902
- Issue date Jun 12, 1990
- Mitsubishi Denki Kabushiki Kaisha
- Michihiro Yamada
- G11 - INFORMATION STORAGE
Information Patent Grant
MIS transistor driven inverter circuit capable of individually cont...
- Patent number 4,931,668
- Issue date Jun 5, 1990
- Mitsubishi Denki Kabushiki Kaisha
- Shigeru Kikuda
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Delay circuit
- Patent number 4,914,326
- Issue date Apr 3, 1990
- Mitsubishi Denki Kabushiki Kaisha
- Shigeru Kikuda
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Substrate bias circuit having substrate bias voltage clamp and oper...
- Patent number 4,904,885
- Issue date Feb 27, 1990
- Mitsubishi Denki Kabushiki Kaisha
- Michihiro Yamada
- G05 - CONTROLLING REGULATING
Information Patent Grant
Dynamic random access memory device with internal refresh
- Patent number 4,870,620
- Issue date Sep 26, 1989
- Mitsubishi Denki Kabushiki Kaisha
- Tadato Yamagata
- G11 - INFORMATION STORAGE
Information Patent Grant
Wafer scale integration semiconductor device having improved chip p...
- Patent number 4,855,613
- Issue date Aug 8, 1989
- Mitsubishi Denki Kabushiki Kaisha
- Michihiro Yamada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor memory having divided bit lines and individual sense...
- Patent number 4,803,663
- Issue date Feb 7, 1989
- Mitsubishi Denki Kabushiki Kaisha
- Hiroshi Miyamoto
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device with bit line sense amplifiers
- Patent number 4,792,927
- Issue date Dec 20, 1988
- Mitsubishi Denki Kabushiki Kaisha
- Hiroshi Miyamoto
- G11 - INFORMATION STORAGE
Information Patent Grant
CMOS reference voltage generator employing separate reference circu...
- Patent number 4,788,455
- Issue date Nov 29, 1988
- Mitsubishi Denki Kabushiki Kaisha
- Shigeru Mori
- G05 - CONTROLLING REGULATING
Information Patent Grant
CMOS dynamic random access memory
- Patent number 4,780,850
- Issue date Oct 25, 1988
- Mitsubishi Denki Kabushiki Kaisha
- Hiroshi Miyamoto
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic ram having folded bit line structure
- Patent number 4,739,500
- Issue date Apr 19, 1988
- Mitsubishi Denki Kabushiki Kaisha
- Hiroshi Miyamoto
- G11 - INFORMATION STORAGE
Information Patent Grant
CMOS decoder circuit resistant to latch-up
- Patent number 4,724,341
- Issue date Feb 9, 1988
- Mitsubishi Denki Kabushiki Kaisha
- Michihiro Yamada
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor memory device
- Patent number 4,689,770
- Issue date Aug 25, 1987
- Mitsubishi Denki Kabushiki Kaisha
- Hiroshi Miyamoto
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic random access memory with hidden refresh control
- Patent number 4,641,281
- Issue date Feb 3, 1987
- Mitsubishi Denki Kabushiki Kaisha
- Koichiro Mashiko
- G11 - INFORMATION STORAGE
Information Patent Grant
Charge coupled semiconductor device storing 2-bit information
- Patent number 4,243,897
- Issue date Jan 6, 1981
- Mitsubishi Denki Kabushiki Kaisha
- Kazuyasu Fujishima
- G11 - INFORMATION STORAGE

Michihiro Yamada

Person

Patents Grantslast 30 patents

Semiconductor memory device and method of data transfer therefor

Semiconductor memory device having multiple memory arrays and inclu...

Semiconductor memory device and method of testing the same

Input circuit of a semiconductor device

Method of fibricating a semiconductor device having a trench

Method of and apparatus for reducing current of semiconductor memor...

Delay circuit employing different threshold FET's

Dynamic random access memory with FET equalization of bit lines

Input protective apparatus of semiconductor device

Electric fuse for a redundancy circuit

Arbiter circuit for processing concurrent requests for access to sh...

Method of and apparatus for reducing current of semiconductor memor...

MIS transistor driven inverter circuit capable of individually cont...

Delay circuit

Substrate bias circuit having substrate bias voltage clamp and oper...

Dynamic random access memory device with internal refresh

Wafer scale integration semiconductor device having improved chip p...

Semiconductor memory having divided bit lines and individual sense...

Semiconductor memory device with bit line sense amplifiers

CMOS reference voltage generator employing separate reference circu...

CMOS dynamic random access memory

Dynamic ram having folded bit line structure

CMOS decoder circuit resistant to latch-up

Semiconductor memory device

Dynamic random access memory with hidden refresh control

Charge coupled semiconductor device storing 2-bit information