Mohamad A. Shaheen

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Substrate having a charged zone in an insulating buried layer
- Patent number 8,735,946
- Issue date May 27, 2014
- Soitec
- Mohamad A Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacking fault and twin blocking barrier for integrating III-V on Si
- Patent number 8,617,945
- Issue date Dec 31, 2013
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Substrate having a charged zone in an insulating buried layer
- Patent number 8,535,996
- Issue date Sep 17, 2013
- Soitec
- Mohamad Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacking fault and twin blocking barrier for integrating III-V on Si
- Patent number 8,143,646
- Issue date Mar 27, 2012
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High mobility tri-gate devices and methods of fabrication
- Patent number 8,084,818
- Issue date Dec 27, 2011
- Intel Corporation
- Mohamad A. Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor buffer architecture for III-V devices on silicon subs...
- Patent number 8,034,675
- Issue date Oct 11, 2011
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor buffer architecture for III-V devices on silicon subs...
- Patent number 7,851,780
- Issue date Dec 14, 2010
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buffer layers for device isolation of devices grown on silicon
- Patent number 7,851,781
- Issue date Dec 14, 2010
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strained semiconductor structures
- Patent number 7,723,749
- Issue date May 25, 2010
- Intel Corporation
- Mohamad A. Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ultra-thin oxide bonding for S1 to S1 dual orientation bonding
- Patent number 7,670,928
- Issue date Mar 2, 2010
- Intel Corporation
- Mohamad A. Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dislocation-free InSb quantum well structure on Si using novel buff...
- Patent number 7,573,059
- Issue date Aug 11, 2009
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual crystal orientation circuit devices on the same substrate
- Patent number 7,569,857
- Issue date Aug 4, 2009
- Intel Corporation
- Peter Tolchinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buffer layers for device isolation of devices grown on silicon
- Patent number 7,494,911
- Issue date Feb 24, 2009
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a silicon-on-insulator (SOI) wafer with an...
- Patent number 7,473,614
- Issue date Jan 6, 2009
- Intel Corporation
- Peter G. Tolchinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of vertically stacking wafers using porous silicon
- Patent number 7,378,331
- Issue date May 27, 2008
- Intel Corporation
- Mohamad Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon on diamond-like carbon devices
- Patent number 7,355,247
- Issue date Apr 8, 2008
- Intel Corporation
- Mohamad A. Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Germanium on insulator fabrication via epitaxial germanium bonding
- Patent number 7,279,369
- Issue date Oct 9, 2007
- Intel Corporation
- Ryan Lei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
III-V and II-VI compounds as template materials for growing germani...
- Patent number 7,202,503
- Issue date Apr 10, 2007
- Intel Corporation
- Loren Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Complete device layer transfer without edge exclusion via direct wa...
- Patent number 7,161,224
- Issue date Jan 9, 2007
- Intel Corporation
- Peter Tolchinsky
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Strained semiconductor structures
- Patent number 7,157,379
- Issue date Jan 2, 2007
- Intel Corporation
- Mohamad A. Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Bonding of substrates
- Patent number 7,148,122
- Issue date Dec 12, 2006
- Intel Corporation
- Mohamad A. Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Arrangements incorporating laser-induced cleaving
- Patent number 7,052,978
- Issue date May 30, 2006
- Intel Corporation
- Mohamad A. Shaheen
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
High mobility tri-gate devices and methods of fabrication
- Patent number 7,042,009
- Issue date May 9, 2006
- Intel Corporation
- Mohamad A. Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming silicon on insulator wafers
- Patent number 6,911,380
- Issue date Jun 28, 2005
- Intel Corporation
- Peter G. Tolchinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Complete device layer transfer without edge exclusion via direct wa...
- Patent number 6,908,027
- Issue date Jun 21, 2005
- Intel Corporation
- Peter Tolchinsky
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Low temperature germanium transfer
- Patent number 6,833,195
- Issue date Dec 21, 2004
- Intel Corporation
- Ryan Lei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Thermally stable crystalline defect-free germanium bonded to silico...
- Patent number 6,645,831
- Issue date Nov 11, 2003
- Intel Corporation
- Mohamad A. Shaheen
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SUBSTRATE HAVING A CHARGED ZONE IN AN INSULATING BURIED LAYER
- Publication number 20140225182
- Publication date Aug 14, 2014
- SOITEC
- Mohamad A. Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE HAVING A CHARGED ZONE IN AN INSULATING BURIED LAYER
- Publication number 20140015023
- Publication date Jan 16, 2014
- SOITEC
- Frederic Allibert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKING FAULT AND TWIN BLOCKING BARRIER FOR INTEGRATING III-V ON SI
- Publication number 20120142166
- Publication date Jun 7, 2012
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR BUFFER ARCHITECTURE FOR III-V DEVICES ON SILICON SUBS...
- Publication number 20110045659
- Publication date Feb 24, 2011
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SUBSTRATE HAVING A CHARGED ZONE IN AN INSULATING BURIED LAYER
- Publication number 20110012200
- Publication date Jan 20, 2011
- S. O. I. Tec Silicon on Insulator Technologies
- Frederic Allibert
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Formation of a multiple crystal orientation substrate
- Publication number 20100155788
- Publication date Jun 24, 2010
- Mohamad A. Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ULTRA-THIN OXIDE BONDING FOR SI TO SI DUAL ORIENTATION BONDING
- Publication number 20100072580
- Publication date Mar 25, 2010
- Intel Corporation
- Mohamad A. Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High mobility tri-gate devices and methods of fabrication
- Publication number 20100065888
- Publication date Mar 18, 2010
- Mohamad A. Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Buffer layers for device isolation of devices grown on silicon
- Publication number 20090218596
- Publication date Sep 3, 2009
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for manufacturing a silicon-on-insulator (SOI) wafer with an...
- Publication number 20090096025
- Publication date Apr 16, 2009
- Peter G. Tolchinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Thin III-V semiconductor films with high electron mobility
- Publication number 20080132081
- Publication date Jun 5, 2008
- Mohamad A. Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual crystal orientation circuit devices on the same substrate
- Publication number 20080079003
- Publication date Apr 3, 2008
- Mohamad A. Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dislocation-free InSb quantum well structure on Si using novel buff...
- Publication number 20080073639
- Publication date Mar 27, 2008
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Buffer layers for device isolation of devices grown on silicon
- Publication number 20080076235
- Publication date Mar 27, 2008
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor buffer architecture for III-V devices on silicon subs...
- Publication number 20080029756
- Publication date Feb 7, 2008
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stacking fault and twin blocking barrier for integrating III-V on Si
- Publication number 20080032478
- Publication date Feb 7, 2008
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Depositing polar materials on non-polar semiconductor substrates
- Publication number 20070238281
- Publication date Oct 11, 2007
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Formation of a multiple crystal orientation substrate
- Publication number 20070215984
- Publication date Sep 20, 2007
- Mohamad A. Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Insulation layer for silicon-on-insulator wafer
- Publication number 20070063279
- Publication date Mar 22, 2007
- Peter G. Tolchinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Strained semiconductor structures
- Publication number 20070007509
- Publication date Jan 11, 2007
- Mohamad A. Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Layer transfer technique
- Publication number 20060286771
- Publication date Dec 21, 2006
- Mohamad Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Silicon on diamond-like carbon devices
- Publication number 20060220028
- Publication date Oct 5, 2006
- Mohamad A. Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods of vertically stacking wafers using porous silicon
- Publication number 20060138627
- Publication date Jun 29, 2006
- Mohamad Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for manufacturing a silicon-on-Insulator (SOI) wafer with an...
- Publication number 20060102988
- Publication date May 18, 2006
- Peter G. Tolchinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Germanium-on-insulator fabrication utilizing wafer bonding
- Publication number 20060049399
- Publication date Mar 9, 2006
- Ryan Lei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Bonding of substrates
- Publication number 20060043483
- Publication date Mar 2, 2006
- Mohamad A. Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Germanium-on-insulator fabrication utilizing wafer bonding
- Publication number 20060046488
- Publication date Mar 2, 2006
- Ryan Lei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High mobility tri-gate devices and methods of fabrication
- Publication number 20060001109
- Publication date Jan 5, 2006
- Mohamad A. Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
III-V and II-VI compounds as template materials for growing germani...
- Publication number 20060001018
- Publication date Jan 5, 2006
- Loren Chow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor wafers with non-standard crystal orientations and met...
- Publication number 20050217560
- Publication date Oct 6, 2005
- Peter G. Tolchinsky
- C30 - CRYSTAL GROWTH

Mohamad A. Shaheen

Person

Patents Grantslast 30 patents

Substrate having a charged zone in an insulating buried layer

Stacking fault and twin blocking barrier for integrating III-V on Si

Substrate having a charged zone in an insulating buried layer

Stacking fault and twin blocking barrier for integrating III-V on Si

High mobility tri-gate devices and methods of fabrication

Semiconductor buffer architecture for III-V devices on silicon subs...

Semiconductor buffer architecture for III-V devices on silicon subs...

Buffer layers for device isolation of devices grown on silicon

Strained semiconductor structures

Ultra-thin oxide bonding for S1 to S1 dual orientation bonding

Dislocation-free InSb quantum well structure on Si using novel buff...

Dual crystal orientation circuit devices on the same substrate

Buffer layers for device isolation of devices grown on silicon

Method for manufacturing a silicon-on-insulator (SOI) wafer with an...

Methods of vertically stacking wafers using porous silicon

Silicon on diamond-like carbon devices

Germanium on insulator fabrication via epitaxial germanium bonding

III-V and II-VI compounds as template materials for growing germani...

Complete device layer transfer without edge exclusion via direct wa...

Strained semiconductor structures

Bonding of substrates

Arrangements incorporating laser-induced cleaving

High mobility tri-gate devices and methods of fabrication

Method of forming silicon on insulator wafers

Complete device layer transfer without edge exclusion via direct wa...

Low temperature germanium transfer

Thermally stable crystalline defect-free germanium bonded to silico...

Patents Applicationslast 30 patents

SUBSTRATE HAVING A CHARGED ZONE IN AN INSULATING BURIED LAYER

SUBSTRATE HAVING A CHARGED ZONE IN AN INSULATING BURIED LAYER

STACKING FAULT AND TWIN BLOCKING BARRIER FOR INTEGRATING III-V ON SI

SEMICONDUCTOR BUFFER ARCHITECTURE FOR III-V DEVICES ON SILICON SUBS...

SUBSTRATE HAVING A CHARGED ZONE IN AN INSULATING BURIED LAYER

Formation of a multiple crystal orientation substrate

ULTRA-THIN OXIDE BONDING FOR SI TO SI DUAL ORIENTATION BONDING

High mobility tri-gate devices and methods of fabrication

Buffer layers for device isolation of devices grown on silicon

Method for manufacturing a silicon-on-insulator (SOI) wafer with an...

Thin III-V semiconductor films with high electron mobility

Dual crystal orientation circuit devices on the same substrate

Dislocation-free InSb quantum well structure on Si using novel buff...

Buffer layers for device isolation of devices grown on silicon

Semiconductor buffer architecture for III-V devices on silicon subs...

Stacking fault and twin blocking barrier for integrating III-V on Si

Depositing polar materials on non-polar semiconductor substrates

Formation of a multiple crystal orientation substrate

Insulation layer for silicon-on-insulator wafer

Strained semiconductor structures

Layer transfer technique

Silicon on diamond-like carbon devices

Methods of vertically stacking wafers using porous silicon

Method for manufacturing a silicon-on-Insulator (SOI) wafer with an...

Germanium-on-insulator fabrication utilizing wafer bonding

Bonding of substrates

Germanium-on-insulator fabrication utilizing wafer bonding

High mobility tri-gate devices and methods of fabrication

III-V and II-VI compounds as template materials for growing germani...

Semiconductor wafers with non-standard crystal orientations and met...