Myron W. Wong

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit decoupling capacitors
- Patent number 9,425,192
- Issue date Aug 23, 2016
- Altera Corporation
- Irfan Rahim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Volatile memory elements with soft error upset immunity
- Patent number 8,289,755
- Issue date Oct 16, 2012
- Altera Corporation
- Irfan Rahim
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuits with fuse programming and sensing circuitry
- Patent number 8,154,942
- Issue date Apr 10, 2012
- Altera Corporation
- Ping Xiao
- G11 - INFORMATION STORAGE
Information Patent Grant
Configuration random access memory
- Patent number 8,030,962
- Issue date Oct 4, 2011
- Altera Corporation
- Irfan Rahim
- G11 - INFORMATION STORAGE
Information Patent Grant
Precharge and discharge of I/O output driver
- Patent number 7,834,667
- Issue date Nov 16, 2010
- Altera Corporation
- Myron Wai Wong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configuration random access memory
- Patent number 7,800,400
- Issue date Sep 21, 2010
- Altera Corporation
- Irfan Rahim
- G11 - INFORMATION STORAGE
Information Patent Grant
Look-up table overdrive circuits
- Patent number 7,800,402
- Issue date Sep 21, 2010
- Altera Corporation
- Irfan Rahim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High voltage tolerance emulation using voltage clamp for oxide stre...
- Patent number 7,733,159
- Issue date Jun 8, 2010
- Altera Corporation
- Rafael Camarota
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Techniques for configuring programmable logic using on-chip nonvola...
- Patent number 7,710,147
- Issue date May 4, 2010
- Altera Corporation
- Thomas H. White
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for configuring programmable logic using on-chip nonvola...
- Patent number 7,375,551
- Issue date May 20, 2008
- Altera Corporation
- Thomas H. White
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structure of a split-gate memory cell
- Patent number 7,236,398
- Issue date Jun 26, 2007
- Altera Corporation
- Richard G. Smolen
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for configuring programmable logic using on-chip nonvola...
- Patent number 7,030,647
- Issue date Apr 18, 2006
- Altera Corporation
- Thomas H. White
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for reducing power consumption in memory cells
- Patent number 6,972,987
- Issue date Dec 6, 2005
- Altera Corporation
- Myron Wai Wong
- G11 - INFORMATION STORAGE
Information Patent Grant
Input buffer with hysteresis option
- Patent number 6,965,251
- Issue date Nov 15, 2005
- Altera Corporation
- Neil Nghia Tran
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method for margin testing single polysilicon EEPROM c...
- Patent number 6,781,883
- Issue date Aug 24, 2004
- Altera Corporation
- Raminda U. Madurawe
- G11 - INFORMATION STORAGE
Information Patent Grant
Charge pump circuits and methods
- Patent number 6,774,707
- Issue date Aug 10, 2004
- Altera Corporation
- Mian Smith
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Cross coupled N-channel negative pump
- Patent number 6,664,846
- Issue date Dec 16, 2003
- Altera Corporation
- Min Maung
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Apparatus and method for margin testing single polysilicon EEPROM c...
- Patent number 6,646,919
- Issue date Nov 11, 2003
- Altera Corporation
- Raminda U. Madurawe
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable logic device input/output circuit configurable as refe...
- Patent number 6,346,827
- Issue date Feb 12, 2002
- Altera Corporation
- Wayne Yeung
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable logic device input/output circuit configurable as refe...
- Patent number 6,335,636
- Issue date Jan 1, 2002
- Altera Corporation
- Wayne Yeung
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and method for isolating noisy signals in an integrated c...
- Patent number 6,279,145
- Issue date Aug 21, 2001
- Altera Corporation
- Myron Wai Wong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method for margin testing single polysilicon EEPROM c...
- Patent number 6,268,623
- Issue date Jul 31, 2001
- Altera Corporation
- Raminda U. Madurawe
- G11 - INFORMATION STORAGE
Information Patent Grant
Reducing I/O noise when leaving programming mode
- Patent number 6,242,941
- Issue date Jun 5, 2001
- Altera Corporation
- W. Bradley Vest
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Output buffer predriver with edge compensation
- Patent number 6,236,237
- Issue date May 22, 2001
- Altera Corporation
- Myron W. Wong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and circuit for reducing output ground and power bounce noise
- Patent number 6,184,703
- Issue date Feb 6, 2001
- Altera Corporation
- William B. Vest
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power compensating voltage reference
- Patent number 6,005,379
- Issue date Dec 21, 1999
- Altera Corporation
- Myron W. Wong
- G05 - CONTROLLING REGULATING
Information Patent Grant
Voltage ramp rate control circuit
- Patent number 5,945,870
- Issue date Aug 31, 1999
- Altera Corporation
- Michael H. Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
Biasing scheme for reducing stress and improving reliability in EEP...
- Patent number 5,905,675
- Issue date May 18, 1999
- Altera Corporation
- Raminda U. Madurawe
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier with individually optimized high and low power modes
- Patent number 5,850,365
- Issue date Dec 15, 1998
- Altera Corporation
- Dirk A. Reese
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for monitoring or forcing an internal node in...
- Patent number 5,821,771
- Issue date Oct 13, 1998
- Altera Corporation
- Rakesh H. Patel
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
CONFIGURATION RANDOM ACCESS MEMORY
- Publication number 20100321984
- Publication date Dec 23, 2010
- Irfan Rahim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTEGRATED CIRCUIT DECOUPLING CAPACITORS
- Publication number 20100148304
- Publication date Jun 17, 2010
- Irfan Rahim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Configuration random access memory
- Publication number 20080169836
- Publication date Jul 17, 2008
- Irfan Rahim
- H03 - BASIC ELECTRONIC CIRCUITRY

Myron W. Wong

Person

Patents Grantslast 30 patents

Integrated circuit decoupling capacitors

Volatile memory elements with soft error upset immunity

Integrated circuits with fuse programming and sensing circuitry

Configuration random access memory

Precharge and discharge of I/O output driver

Configuration random access memory

Look-up table overdrive circuits

High voltage tolerance emulation using voltage clamp for oxide stre...

Techniques for configuring programmable logic using on-chip nonvola...

Techniques for configuring programmable logic using on-chip nonvola...

Structure of a split-gate memory cell

Techniques for configuring programmable logic using on-chip nonvola...

Techniques for reducing power consumption in memory cells

Input buffer with hysteresis option

Apparatus and method for margin testing single polysilicon EEPROM c...

Charge pump circuits and methods

Cross coupled N-channel negative pump

Apparatus and method for margin testing single polysilicon EEPROM c...

Programmable logic device input/output circuit configurable as refe...

Programmable logic device input/output circuit configurable as refe...

Apparatus and method for isolating noisy signals in an integrated c...

Apparatus and method for margin testing single polysilicon EEPROM c...

Reducing I/O noise when leaving programming mode

Output buffer predriver with edge compensation

Method and circuit for reducing output ground and power bounce noise

Power compensating voltage reference

Voltage ramp rate control circuit

Biasing scheme for reducing stress and improving reliability in EEP...

Sense amplifier with individually optimized high and low power modes

Method and apparatus for monitoring or forcing an internal node in...

Patents Applicationslast 30 patents

CONFIGURATION RANDOM ACCESS MEMORY

INTEGRATED CIRCUIT DECOUPLING CAPACITORS

Configuration random access memory