Nancy M. Zelick

Person

Beaverton, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Ingaas epi structure and wet etch process for enabling III-v GAA in...
- Patent number 11,631,737
- Issue date Apr 18, 2023
- Intel Corporation
- Sanaz K. Gardner
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Channel layer formed in an art trench
- Patent number 11,164,974
- Issue date Nov 2, 2021
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fermi-level unpinning structures for semiconductive devices, proces...
- Patent number 10,756,198
- Issue date Aug 25, 2020
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Two-dimensional condensation for uniaxially strained semiconductor...
- Patent number 10,304,929
- Issue date May 28, 2019
- Intel Corporation
- Jack T. Kavalieros
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-silicon device heterolayers on patterned silicon substrate for...
- Patent number 10,249,490
- Issue date Apr 2, 2019
- Intel Corporation
- Niti Goel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nanoscale structure with epitaxial film having a recessed bottom po...
- Patent number 9,865,684
- Issue date Jan 9, 2018
- Intel Corporation
- Benjamin Chu-Kung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fermi-level unpinning structures for semiconductive devices, proces...
- Patent number 9,768,269
- Issue date Sep 19, 2017
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Two-dimensional condensation for uniaxially strained semiconductor...
- Patent number 9,711,598
- Issue date Jul 18, 2017
- Intel Corporation
- Jack T. Kavalieros
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-planar device having uniaxially strained semiconductor body and...
- Patent number 9,680,013
- Issue date Jun 13, 2017
- Intel Corporation
- Stephen M. Cea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-silicon device heterolayers on patterned silicon substrate for...
- Patent number 9,640,537
- Issue date May 2, 2017
- Intel Corporation
- Niti Goel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Two-dimensional condensation for uniaxially strained semiconductor...
- Patent number 9,419,140
- Issue date Aug 16, 2016
- Intel Corporation
- Jack T. Kavalieros
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lattice mismatched hetero-epitaxial film
- Patent number 9,391,181
- Issue date Jul 12, 2016
- Intel Corporation
- Benjamin Chu-Kung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Two-dimensional condensation for uniaxially strained semiconductor...
- Patent number 9,159,835
- Issue date Oct 13, 2015
- Intel Corporation
- Jack T. Kavalieros
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Epitaxial film on nanoscale structure
- Patent number 9,029,835
- Issue date May 12, 2015
- Intel Corporation
- Benjamin Chu-King
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fermi-level unpinning structures for semiconductive devices, proces...
- Patent number 8,878,363
- Issue date Nov 4, 2014
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Defect transferred and lattice mismatched epitaxial film
- Patent number 8,872,225
- Issue date Oct 28, 2014
- Intel Corporation
- Benjamin Chu-Kung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-planar device having uniaxially strained semiconductor body and...
- Patent number 8,558,279
- Issue date Oct 15, 2013
- Intel Corporation
- Stephen M. Cea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Polish to remove topography in sacrificial gate layer prior to gate...
- Patent number 8,334,184
- Issue date Dec 18, 2012
- Intel Corporation
- Joseph M. Steigerwald
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Two-dimensional condensation for uniaxially strained semiconductor...
- Patent number 8,211,772
- Issue date Jul 3, 2012
- Intel Corporation
- Jack T. Kavalieros
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-planar pMOS structure with a strained channel region and an int...
- Patent number 7,960,794
- Issue date Jun 14, 2011
- Intel Corporation
- Brian S Doyle
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Non-planar pMOS structure with a strained channel region and an int...
- Patent number 7,348,284
- Issue date Mar 25, 2008
- Intel Corporation
- Brian S Doyle
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
LOW-RESISTANCE AND THERMALLY STABLE CONTACTS WITH PHOSPHIDE OR ARSE...
- Publication number 20240006506
- Publication date Jan 4, 2024
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW-RESISTANCE AND THERMALLY STABLE CONTACTS WITH BORIDE, INDIUM, O...
- Publication number 20240006533
- Publication date Jan 4, 2024
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CAPPING SOURCE AND DRAIN REGIONS OF TRANSISTORS TO PREVENT DIFFUSIO...
- Publication number 20240006488
- Publication date Jan 4, 2024
- Intel Corporation
- Nazila Haratipour
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOURCE AND DRAIN REFRACTORY METAL CAP
- Publication number 20240006494
- Publication date Jan 4, 2024
- Intel Corporation
- Nazila Haratipour
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTACT OVER ACTIVE GATE STRUCTURES WITH TRENCH CONTACT LAYERS FOR...
- Publication number 20230197804
- Publication date Jun 22, 2023
- Nazila HARATIPOUR
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IMPROVED CHANNEL LAYER FORMED IN AN ART TRENCH
- Publication number 20200220017
- Publication date Jul 9, 2020
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FERMI-LEVEL UNPINNING STRUCTURES FOR SEMICONDUCTIVE DEVICES, PROCES...
- Publication number 20170365681
- Publication date Dec 21, 2017
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THIN CHANNEL REGION ON WIDE SUBFIN
- Publication number 20170323963
- Publication date Nov 9, 2017
- Sanaz K. GARDNER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Uniform Layers Formed with Aspect Ratio Trench Based Processes
- Publication number 20170317187
- Publication date Nov 2, 2017
- Sanaz K. GARDNER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TWO-DIMENSIONAL CONDENSATION FOR UNIAXIALLY STRAINED SEMICONDUCTOR...
- Publication number 20170317172
- Publication date Nov 2, 2017
- Intel Corporation
- Jack T. Kavalieros
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INGAAS EPI STRUCTURE AND WET ETCH PROCESS FOR ENABLING III-V GAA IN...
- Publication number 20170263706
- Publication date Sep 14, 2017
- Sanaz K. GARDNER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-SILICON DEVICE HETEROLAYERS ON PATTERNED SILICON SUBSTRATE FOR...
- Publication number 20170186598
- Publication date Jun 29, 2017
- Intel Corporation
- Niti GOEL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TWO-DIMENSIONAL CONDENSATION FOR UNIAXIALLY STRAINED SEMICONDUCTOR...
- Publication number 20160329403
- Publication date Nov 10, 2016
- Intel Corporation
- Jack T. Kavalieros
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-SILICON DEVICE HETEROLAYERS ON PATTERNED SILICON SUBSTRATE FOR...
- Publication number 20160211263
- Publication date Jul 21, 2016
- Intel Corporation
- Niti GOEL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non-Planar Semiconductor Devices having Multi-Layered Compliant Sub...
- Publication number 20160190319
- Publication date Jun 30, 2016
- JACK T. KAVALIEROS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TWO-DIMENSIONAL CONDENSATION FOR UNIAXIALLY STRAINED SEMICONDUCTOR...
- Publication number 20160049513
- Publication date Feb 18, 2016
- Jack T. Kavalieros
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Epitaxial Film On Nanoscale Structure
- Publication number 20150249131
- Publication date Sep 3, 2015
- Intel Corporation
- BENJAMIN CHU-KUNG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FERMI-LEVEL UNPINNING STRUCTURES FOR SEMICONDUCTIVE DEVICES, PROCES...
- Publication number 20150001644
- Publication date Jan 1, 2015
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Defect Transferred and Lattice Mismatched Epitaxial Film
- Publication number 20140175512
- Publication date Jun 26, 2014
- BENJAMIN CHU-KUNG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EPITAXIAL FILM ON NANOSCALE STRUCTURE
- Publication number 20140175379
- Publication date Jun 26, 2014
- BENJAMIN CHU-KUNG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Lattice Mismatched Hetero-Epitaxial Film
- Publication number 20140175509
- Publication date Jun 26, 2014
- BENJAMIN CHU-KUNG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non-Planar Device Having Uniaxially Strained Semiconductor Body and...
- Publication number 20140070273
- Publication date Mar 13, 2014
- Stephen M. Cea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TWO-DIMENSIONAL CONDENSATION FOR UNIAXIALLY STRAINED SEMICONDUCTOR...
- Publication number 20120241818
- Publication date Sep 27, 2012
- Jack T. Kavalieros
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non-planar device having uniaxially strained semiconductor body and...
- Publication number 20120074464
- Publication date Mar 29, 2012
- Stephen M. Cea
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TWO-DIMENSIONAL CONDENSATION FOR UNIAXIALLY STRAINED SEMICONDUCTOR...
- Publication number 20110147811
- Publication date Jun 23, 2011
- Jack T. Kavalieros
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POLISH TO REMOVE TOPOGRAPHY IN SACRIFICIAL GATE LAYER PRIOR TO GATE...
- Publication number 20110147812
- Publication date Jun 23, 2011
- Joseph M. Steigerwald
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Fermi-level unpinning structures for semiconductive devices, proces...
- Publication number 20100327377
- Publication date Dec 30, 2010
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non-planar pMOS structure with a strained channel region and an int...
- Publication number 20080169512
- Publication date Jul 17, 2008
- Brian S. Doyle
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEALING SPACER TO REDUCE OR ELIMINATE LATERAL OXIDATION OF A HIGH-K...
- Publication number 20070262399
- Publication date Nov 15, 2007
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non-planar pMOS structure with a strained channel region and an int...
- Publication number 20060033095
- Publication date Feb 16, 2006
- Brian S. Doyle
- H01 - BASIC ELECTRIC ELEMENTS

Nancy M. Zelick

Person

Patents Grantslast 30 patents

Ingaas epi structure and wet etch process for enabling III-v GAA in...

Channel layer formed in an art trench

Fermi-level unpinning structures for semiconductive devices, proces...

Two-dimensional condensation for uniaxially strained semiconductor...

Non-silicon device heterolayers on patterned silicon substrate for...

Nanoscale structure with epitaxial film having a recessed bottom po...

Fermi-level unpinning structures for semiconductive devices, proces...

Two-dimensional condensation for uniaxially strained semiconductor...

Non-planar device having uniaxially strained semiconductor body and...

Non-silicon device heterolayers on patterned silicon substrate for...

Two-dimensional condensation for uniaxially strained semiconductor...

Lattice mismatched hetero-epitaxial film

Two-dimensional condensation for uniaxially strained semiconductor...

Epitaxial film on nanoscale structure

Fermi-level unpinning structures for semiconductive devices, proces...

Defect transferred and lattice mismatched epitaxial film

Non-planar device having uniaxially strained semiconductor body and...

Polish to remove topography in sacrificial gate layer prior to gate...

Two-dimensional condensation for uniaxially strained semiconductor...

Non-planar pMOS structure with a strained channel region and an int...

Non-planar pMOS structure with a strained channel region and an int...

Patents Applicationslast 30 patents

LOW-RESISTANCE AND THERMALLY STABLE CONTACTS WITH PHOSPHIDE OR ARSE...

LOW-RESISTANCE AND THERMALLY STABLE CONTACTS WITH BORIDE, INDIUM, O...

CAPPING SOURCE AND DRAIN REGIONS OF TRANSISTORS TO PREVENT DIFFUSIO...

SOURCE AND DRAIN REFRACTORY METAL CAP

CONTACT OVER ACTIVE GATE STRUCTURES WITH TRENCH CONTACT LAYERS FOR...

IMPROVED CHANNEL LAYER FORMED IN AN ART TRENCH

FERMI-LEVEL UNPINNING STRUCTURES FOR SEMICONDUCTIVE DEVICES, PROCES...

THIN CHANNEL REGION ON WIDE SUBFIN

Uniform Layers Formed with Aspect Ratio Trench Based Processes

TWO-DIMENSIONAL CONDENSATION FOR UNIAXIALLY STRAINED SEMICONDUCTOR...

INGAAS EPI STRUCTURE AND WET ETCH PROCESS FOR ENABLING III-V GAA IN...

NON-SILICON DEVICE HETEROLAYERS ON PATTERNED SILICON SUBSTRATE FOR...

TWO-DIMENSIONAL CONDENSATION FOR UNIAXIALLY STRAINED SEMICONDUCTOR...

NON-SILICON DEVICE HETEROLAYERS ON PATTERNED SILICON SUBSTRATE FOR...

Non-Planar Semiconductor Devices having Multi-Layered Compliant Sub...

TWO-DIMENSIONAL CONDENSATION FOR UNIAXIALLY STRAINED SEMICONDUCTOR...

Epitaxial Film On Nanoscale Structure

FERMI-LEVEL UNPINNING STRUCTURES FOR SEMICONDUCTIVE DEVICES, PROCES...

Defect Transferred and Lattice Mismatched Epitaxial Film

EPITAXIAL FILM ON NANOSCALE STRUCTURE

Lattice Mismatched Hetero-Epitaxial Film

Non-Planar Device Having Uniaxially Strained Semiconductor Body and...

TWO-DIMENSIONAL CONDENSATION FOR UNIAXIALLY STRAINED SEMICONDUCTOR...

Non-planar device having uniaxially strained semiconductor body and...

TWO-DIMENSIONAL CONDENSATION FOR UNIAXIALLY STRAINED SEMICONDUCTOR...

POLISH TO REMOVE TOPOGRAPHY IN SACRIFICIAL GATE LAYER PRIOR TO GATE...

Fermi-level unpinning structures for semiconductive devices, proces...

Non-planar pMOS structure with a strained channel region and an int...

SEALING SPACER TO REDUCE OR ELIMINATE LATERAL OXIDATION OF A HIGH-K...

Non-planar pMOS structure with a strained channel region and an int...