Navneet Jain

Person

Milpitas, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor structure including sectioned well region
- Patent number 12,046,603
- Issue date Jul 23, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Navneet Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure including a cross-bar router and method
- Patent number 12,027,226
- Issue date Jul 2, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Venkatesh P. Gopinath
- G11 - INFORMATION STORAGE
Information Patent Grant
Back bias control for always-on circuit section enabling leakage re...
- Patent number 11,979,145
- Issue date May 7, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Navneet K. Jain
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Deep nwell contact structures
- Patent number 11,929,399
- Issue date Mar 12, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Navneet K. Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method for delaying of data signal from pulse latch w...
- Patent number 11,894,845
- Issue date Feb 6, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Navneet K. Jain
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable delay circuit including threshold-voltage programmable...
- Patent number 11,855,642
- Issue date Dec 26, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Navneet K. Jain
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Well contact cell with doped tap region separated from active regio...
- Patent number 10,909,298
- Issue date Feb 2, 2021
- GLOBALFOUNDRIES Dresden Module One Limited Liability Company & Co. KG
- Nigel Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structure and method for flexible power staple insertion
- Patent number 10,658,294
- Issue date May 19, 2020
- GLOBALFOUNDRIES Inc.
- Juhan Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structure and method for flexible power staple insertion
- Patent number 10,366,954
- Issue date Jul 30, 2019
- GLOBALFOUNDRIES Inc.
- Juhan Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Context aware processing to resolve strong spacing effects due to s...
- Patent number 10,360,334
- Issue date Jul 23, 2019
- GLOBALFOUNDRIES Inc.
- Navneet Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Calibration devices for I/O driver circuits having switches biased...
- Patent number 10,333,497
- Issue date Jun 25, 2019
- GLOBALFOUNDRIES Inc.
- Anil Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-chip voltage generator for back-biasing field effect transistors...
- Patent number 10,303,196
- Issue date May 28, 2019
- GLOBALFOUNDRIES Inc.
- Navneet Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Special construct for continuous non-uniform active region FinFET s...
- Patent number 10,199,378
- Issue date Feb 5, 2019
- GLOBALFOUNDRIES Inc.
- Navneet Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Antenna diode circuit for manufacturing of semiconductor devices
- Patent number 10,096,595
- Issue date Oct 9, 2018
- GLOBALFOUNDRIES Inc.
- Juhan Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Contacting SOI subsrates
- Patent number 10,068,918
- Issue date Sep 4, 2018
- GLOBALFOUNDRIES Inc.
- Christian Haufe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Special construct for continuous non-uniform active region FinFET s...
- Patent number 9,893,063
- Issue date Feb 13, 2018
- GLOBALFOUNDRIES Inc.
- Navneet Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Special construct for continuous non-uniform RX FinFET standard cells
- Patent number 9,634,003
- Issue date Apr 25, 2017
- GLOBALFOUNDRIES Inc.
- Navneet Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Measuring setup and hold times using a virtual delay
- Patent number 9,479,179
- Issue date Oct 25, 2016
- GLOBALFOUNDRIES Inc.
- Andy T. Nguyen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Special constructs for continuous non-uniform active region FinFET...
- Patent number 9,337,099
- Issue date May 10, 2016
- GLOBALFOUNDRIES Inc.
- Navneet Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of using a trench salicide routing layer
- Patent number 9,196,548
- Issue date Nov 24, 2015
- GLOBALFOUNDRIES Inc.
- Mahbub Rashed
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrating optimal planar and three-dimensional semiconductor desi...
- Patent number 8,966,423
- Issue date Feb 24, 2015
- GLOBALFOUNDRIES Inc.
- Navneet Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parameterized cell for planar and finFET technology design
- Patent number 8,904,324
- Issue date Dec 2, 2014
- GLOBALFOUNDRIES Inc.
- Navneet Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing timing-closed FinFET designs from planar designs
- Patent number 8,689,154
- Issue date Apr 1, 2014
- GLOBALFOUNDRIES Inc.
- Mahbub Rashed
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
NANOSHEET STRUCTURES WITH TUNABLE CHANNELS AND INNER SIDEWALL SPACERS
- Publication number 20240387668
- Publication date Nov 21, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Hong Yu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR PERFORMING DESIGN RULE CHECKS
- Publication number 20240370632
- Publication date Nov 7, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Romain FEUILLETTE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-FIN FIN-TYPE FIELD EFFECT TRANSISTOR WITH FINE-TUNED EFFECTIV...
- Publication number 20240347638
- Publication date Oct 17, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Navneet K. Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ANTENNA STRUCTURE
- Publication number 20240304616
- Publication date Sep 12, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Xuelian ZHU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE INCLUDING SECTIONED WELL REGION
- Publication number 20240282776
- Publication date Aug 22, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Navneet Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD TO GROUND REFERENCE VOLTAGE GENERATOR
- Publication number 20240274161
- Publication date Aug 15, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Dzung T. Tran
- G11 - INFORMATION STORAGE
Information Patent Application
STANDARD CELL AND IC STRUCTURE WITH TRENCH ISOLATION THROUGH ACTIVE...
- Publication number 20240274603
- Publication date Aug 15, 2024
- GLOBALFOUNDRIES U.S. Inc.
- David Charles Pritchard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-VOLATILE CURRENT MIRROR CIRCUIT WITH PROGRAMMABLE TRANSISTOR
- Publication number 20240241534
- Publication date Jul 18, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Navneet K. Jain
- G05 - CONTROLLING REGULATING
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE WITH MULTI-ROW CELL FOR ACCOMMODATING...
- Publication number 20240222356
- Publication date Jul 4, 2024
- GLOBALFOUNDRIES U.S. Inc.
- James P. Mazza
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NON-VOLATILE STATIC RANDOM ACCESS MEMORY BIT CELLS WITH FERROELECTR...
- Publication number 20240194253
- Publication date Jun 13, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Pirooz Parvarandeh
- G11 - INFORMATION STORAGE
Information Patent Application
TRANSISTOR ARRAYS WITH CONTROLLABLE GATE VOLTAGE
- Publication number 20240194535
- Publication date Jun 13, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Venkatesh P. Gopinath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD FOR DELAYING OF DATA SIGNAL FROM PULSE LATCH W...
- Publication number 20240072771
- Publication date Feb 29, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Navneet K. Jain
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE WITH CELLS HAVING ASYMMETRIC POWER RAIL
- Publication number 20240021621
- Publication date Jan 18, 2024
- GLOBALFOUNDRIES U.S. Inc.
- James P. Mazza
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE INCLUDING A CROSS-BAR ROUTER AND METHOD
- Publication number 20240005963
- Publication date Jan 4, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Venkatesh P. Gopinath
- G11 - INFORMATION STORAGE
Information Patent Application
LOCAL INTERCONNECT POWER RAILS AND UPPER POWER RAILS
- Publication number 20230335484
- Publication date Oct 19, 2023
- GLOBALFOUNDRIES U.S. Inc.
- James P. MAZZA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEEP NWELL CONTACT STRUCTURES
- Publication number 20230282707
- Publication date Sep 7, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Navneet K. Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CELL LAYOUTS
- Publication number 20230268335
- Publication date Aug 24, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Juhan KIM
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM AND METHOD EMPLOYING POWER-OPTIMIZED TIMING CLOSURE
- Publication number 20230267259
- Publication date Aug 24, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Navneet Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR STRUCTURE INCLUDING SECTIONED WELL REGION
- Publication number 20230163134
- Publication date May 25, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Navneet Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD FOR FLEXIBLE POWER STAPLE INSERTION
- Publication number 20190333853
- Publication date Oct 31, 2019
- GLOBALFOUNDRIES INC.
- Juhan Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTEXT AWARE PROCESSING TO RESOLVE STRONG SPACING EFFECTS DUE TO S...
- Publication number 20180225406
- Publication date Aug 9, 2018
- GLOBALFOUNDRIES INC.
- Navneet Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPECIAL CONSTRUCT FOR CONTINUOUS NON-UNIFORM ACTIVE REGION FINFET S...
- Publication number 20180122804
- Publication date May 3, 2018
- GLOBALFOUNDRIES INC.
- Navneet JAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STANDARD CELL LAYOUT AND METHOD OF ARRANGING A PLURALITY OF STANDAR...
- Publication number 20170358565
- Publication date Dec 14, 2017
- GLOBALFOUNDRIES INC.
- Ulrich Hensel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SPECIAL CONSTRUCT FOR CONTINUOUS NON-UNIFORM ACTIVE REGION FINFET S...
- Publication number 20170141109
- Publication date May 18, 2017
- GLOBALFOUNDRIES INC.
- Navneet JAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ANTENNA DIODE CIRCUIT FOR MANUFACTURING OF SEMICONDUCTOR DEVICES
- Publication number 20170125403
- Publication date May 4, 2017
- GLOBALFOUNDRIES INC.
- Juhan Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTACTING SOI SUBSTRATES
- Publication number 20170104005
- Publication date Apr 13, 2017
- GLOBALFOUNDRIES INC.
- Christian Haufe
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SPECIAL CONSTRUCT FOR CONTINUOUS NON-UNIFORM RX FINFET STANDARD CELLS
- Publication number 20160225763
- Publication date Aug 4, 2016
- GLOBALFOUNDRIES INC.
- Navneet JAIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEASURING SETUP AND HOLD TIMES USING A VIRTUAL DELAY
- Publication number 20150309113
- Publication date Oct 29, 2015
- GLOBALFOUNDRIES INC.
- Andy T. NGUYEN
- G01 - MEASURING TESTING
Information Patent Application
PARAMETERIZED CELL FOR PLANAR AND FINFET TECHNOLOGY DESIGN
- Publication number 20140282323
- Publication date Sep 18, 2014
- GLOBALFOUNDRIES INC.
- Navneet Jain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATING OPTIMAL PLANAR AND THREE-DIMENSIONAL SEMICONDUCTOR DESI...
- Publication number 20140258960
- Publication date Sep 11, 2014
- GLOBALFOUNDRIES INC.
- Navneet Jain
- G06 - COMPUTING CALCULATING COUNTING

Navneet Jain

Person

Patents Grantslast 30 patents

Semiconductor structure including sectioned well region

Structure including a cross-bar router and method

Back bias control for always-on circuit section enabling leakage re...

Deep nwell contact structures

Structure and method for delaying of data signal from pulse latch w...

Programmable delay circuit including threshold-voltage programmable...

Well contact cell with doped tap region separated from active regio...

Structure and method for flexible power staple insertion

Structure and method for flexible power staple insertion

Context aware processing to resolve strong spacing effects due to s...

Calibration devices for I/O driver circuits having switches biased...

On-chip voltage generator for back-biasing field effect transistors...

Special construct for continuous non-uniform active region FinFET s...

Antenna diode circuit for manufacturing of semiconductor devices

Contacting SOI subsrates

Special construct for continuous non-uniform active region FinFET s...

Special construct for continuous non-uniform RX FinFET standard cells

Measuring setup and hold times using a virtual delay

Special constructs for continuous non-uniform active region FinFET...

Methods of using a trench salicide routing layer

Integrating optimal planar and three-dimensional semiconductor desi...

Parameterized cell for planar and finFET technology design

Providing timing-closed FinFET designs from planar designs

Patents Applicationslast 30 patents

NANOSHEET STRUCTURES WITH TUNABLE CHANNELS AND INNER SIDEWALL SPACERS

METHOD FOR PERFORMING DESIGN RULE CHECKS

MULTI-FIN FIN-TYPE FIELD EFFECT TRANSISTOR WITH FINE-TUNED EFFECTIV...

ANTENNA STRUCTURE

SEMICONDUCTOR STRUCTURE INCLUDING SECTIONED WELL REGION

STRUCTURE AND METHOD TO GROUND REFERENCE VOLTAGE GENERATOR

STANDARD CELL AND IC STRUCTURE WITH TRENCH ISOLATION THROUGH ACTIVE...

NON-VOLATILE CURRENT MIRROR CIRCUIT WITH PROGRAMMABLE TRANSISTOR

INTEGRATED CIRCUIT STRUCTURE WITH MULTI-ROW CELL FOR ACCOMMODATING...

NON-VOLATILE STATIC RANDOM ACCESS MEMORY BIT CELLS WITH FERROELECTR...

TRANSISTOR ARRAYS WITH CONTROLLABLE GATE VOLTAGE

STRUCTURE AND METHOD FOR DELAYING OF DATA SIGNAL FROM PULSE LATCH W...

INTEGRATED CIRCUIT STRUCTURE WITH CELLS HAVING ASYMMETRIC POWER RAIL

STRUCTURE INCLUDING A CROSS-BAR ROUTER AND METHOD

LOCAL INTERCONNECT POWER RAILS AND UPPER POWER RAILS

DEEP NWELL CONTACT STRUCTURES

CELL LAYOUTS

SYSTEM AND METHOD EMPLOYING POWER-OPTIMIZED TIMING CLOSURE

SEMICONDUCTOR STRUCTURE INCLUDING SECTIONED WELL REGION

STRUCTURE AND METHOD FOR FLEXIBLE POWER STAPLE INSERTION

CONTEXT AWARE PROCESSING TO RESOLVE STRONG SPACING EFFECTS DUE TO S...

SPECIAL CONSTRUCT FOR CONTINUOUS NON-UNIFORM ACTIVE REGION FINFET S...

STANDARD CELL LAYOUT AND METHOD OF ARRANGING A PLURALITY OF STANDAR...

SPECIAL CONSTRUCT FOR CONTINUOUS NON-UNIFORM ACTIVE REGION FINFET S...

ANTENNA DIODE CIRCUIT FOR MANUFACTURING OF SEMICONDUCTOR DEVICES

CONTACTING SOI SUBSTRATES

SPECIAL CONSTRUCT FOR CONTINUOUS NON-UNIFORM RX FINFET STANDARD CELLS

MEASURING SETUP AND HOLD TIMES USING A VIRTUAL DELAY

PARAMETERIZED CELL FOR PLANAR AND FINFET TECHNOLOGY DESIGN

INTEGRATING OPTIMAL PLANAR AND THREE-DIMENSIONAL SEMICONDUCTOR DESI...