Patent Application
20240347638
The present disclosure relates fin-type field effect transistors (FINFETs) and, more particularly, to embodiments of a multi-fin FINFET and a method of forming a multi-fin FINFET.
A single-fin FINFET includes a semiconductor fin and a gate, the latter of which is adjacent to the top surface and opposing side walls of the semiconductor fin at a channel region. The effective channel width (Weff) is equal to twice the fin height (h) plus the top surface fin width (w) at the channel region (i.e., Weff=2h+w). At some FINFET technology nodes, integrated circuit (IC) designers do not have the option of using single-fin FINFETs because of significant process variations that can lead to performance degradation. So, multi-fin FINFETs are used instead. In such multi-fin FINFETs, each semiconductor fin has essentially the same dimensions and Weff=Σ(2h+w); where h is the fin height, where w is the top surface fin width, and where i is the number of semiconductor fins. Use of multi-fin FINFETs makes it difficult to fine tune Weff. For example, a designer cannot include, within an IC design, a multi-fin FINFET with a Weff<Σ(2h+w)2 (e.g., with a Weff=2h+w).
Disclosed herein are embodiments of a semiconductor structure. The
semiconductor structure can include at least two semiconductor fins including a first semiconductor fin and a second semiconductor fin parallel to the first semiconductor fin. The first semiconductor fin can have a first top surface and first opposing sidewalls (including a first inner sidewall and a first outer sidewall opposite the first inner sidewall). The second semiconductor fin can have a second top surface and second opposing sidewalls (including a second inner sidewall facing the first inner sidewall of the first semiconductor fin and a second outer sidewall opposite the second inner sidewall). The semiconductor structure can further include a first isolation structure, which is positioned laterally immediately adjacent (i.e., abutting) the first outer sidewall of the first semiconductor fin, and a gate, which is positioned laterally immediately adjacent to the first inner sidewall of the first semiconductor fin opposite the first isolation structure and which further extends over the first top surface such that it is also positioned laterally immediately adjacent to the first isolation structure.
Some disclosed embodiments of the semiconductor structure can include more than two semiconductor fins including a first semiconductor fin, a second semiconductor fin, and at least one additional semiconductor fin between and parallel to the first semiconductor fin and the second semiconductor fin. The first semiconductor fin can have a first top surface and first opposing sidewalls (including a first inner sidewall and a first outer sidewall opposite the first inner sidewall). The second semiconductor fin can have a second top surface and second opposing sidewalls (including a second inner sidewall and a second outer sidewall opposite the second inner sidewall). Each additional semiconductor fin can have an additional top surface and additional opposing sidewalls. As described in greater detail below, the first inner sidewall of the first semiconductor fin and the second inner sidewall of the second semiconductor can each face a different additional opposing sidewall (e.g., of the same additional semiconductor fin or, alternatively, of different additional semiconductor fins). The semiconductor structure can further include a first isolation structure, which is positioned laterally immediately adjacent (i.e., abutting) the first outer sidewall of the first semiconductor fin. The semiconductor structure can further include a gate, which is positioned laterally immediately adjacent to the first inner sidewall of the first semiconductor fin opposite the first isolation structure and which further extends over the first top surface such that it is also positioned laterally immediately adjacent to the first isolation structure. The gate can further be positioned laterally immediately adjacent to the additional opposing sidewalls and the additional top surface of each additional semiconductor fin and immediately adjacent to at least the second inner sidewall and the second top surface of the second semiconductor fin.
Also disclosed herein are method embodiments for forming the disclosed semiconductor structures. For example, a disclosed method can include forming multiple semiconductor fins. The multiple semiconductor fins can include at least a first semiconductor fin and a second semiconductor fin parallel to the first semiconductor fin. The first semiconductor fin can have a first top surface and first opposing sidewalls (including a first inner sidewall and a first outer sidewall opposite the first inner sidewall). The second semiconductor fin can have a second top surface and second opposing sidewalls (including a second inner sidewall facing the first inner sidewall of the first semiconductor fin) and a second outer sidewall opposite the second inner sidewall. The method can further include forming a first isolation structure positioned laterally immediately adjacent to the first outer sidewall. The method can further include forming a gate positioned laterally immediately adjacent to the first inner sidewall of the first semiconductor fin opposite the first isolation structure and further extending over the first top surface of the first semiconductor fin to the first isolation structure.
The present disclosure will be better understood from the following detailed description with reference to the drawings, which are not necessarily drawn to scale and in which:
As mentioned above, a single-fin FINFET includes a semiconductor fin and a gate, which is adjacent to the top surface and opposing side walls of the semiconductor fin at a channel region. The effective channel width (Weff) is equal to twice the fin height (h) plus the top surface fin width (w) at the channel region (i.e., Weff=2h+w). At some FINFET technology nodes, integrated circuit (IC) designers do not have the option of using single-fin FINFETs because of significant process variations that can lead to performance degradation. So, multi-fin FINFETs are used instead. In such multi-fin FINFETs, each semiconductor fin has essentially the same dimensions and Weff=Σ(2h+w)i, where h is the fin height, where w is the top surface fin width, and where i is the number of semiconductor fins. As a result, it can be difficult to fine tune Weff. For example, a designer cannot include, within an IC design, a multi-fin FINFET with a Weff<Σ(2h+w)2 (e.g., with a Weff=2h+w).
In view of the foregoing, disclosed herein are embodiments of a semiconductor structure including a multi-fin FINFET with a fine-tuned Weff (e.g., a multi-fin FINFET where Weff≠Σ(2h+w)i, such as a two-fin FINFET where Weff=2h+w). The multi-fin FINFET can include a first semiconductor fin, a second semiconductor fin, and, optionally, one or more additional semiconductor fins between and parallel to the first and second semiconductor fins. Each semiconductor fin can include a channel region between source/drain regions. A first isolation structure can be positioned laterally immediately adjacent to an outer sidewall of the first semiconductor fin at the channel region. Optionally, the first isolation structure can further be seated within a groove in that outer sidewall so that the width of the first semiconductor fin at the channel region is effectively reduced (e.g., by half). A gate can be immediately adjacent to an inner sidewall of the first semiconductor fin at the channel region and can extend over the top surface of the first semiconductor fin to the isolation structure. The gate can further be immediately adjacent to the opposing sidewalls and top surface of each additional semiconductor fin(s) (if any) and at least an inner sidewall and top surface of the second semiconductor fin. In some embodiments, a second isolation structure can be positioned laterally immediately adjacent to an outer sidewall of the second semiconductor fin and the gate can extend over the second top surface of the second semiconductor fin to the second isolation structure. Optionally, the second isolation structure can be seated within a groove in that outer sidewall so that the width of the second semiconductor fin at the channel region is effectively reduced (e.g., again by half). In other embodiments, the gate can be immediately adjacent to both the inner and outer sidewalls and the top surface of the second semiconductor fin. Thus, in the disclosed embodiments, the portion of Weff of the FINFET attributable to the first semiconductor fin and, optionally, the portion of Weff of the FINFET attributable to the second semiconductor fin are each reduced (e.g., to h+w, to h+½w, or to h+ some other fraction of w), while the portion of Weff attributable to each additional semiconductor fin (if any) between the first semiconductor fin and the second semiconductor fin remains at 2h+w.
Referring to
Referring to
The semiconductor fins can include a first semiconductor fin 111a, which has first opposing sidewalls (including a first inner sidewall 121a and a first outer sidewall 122a opposite first inner sidewall 121a) and a first top surface 123a. The semiconductor fins can include a second semiconductor fin 111b, which is parallel to first semiconductor fin 111a and which has second opposing sidewalls (including a second inner sidewall 121b and a second outer sidewall 122b) and a second top surface 123b. In the case of a two-fin structure (e.g., see the semiconductor structures 100.1-100.5), first inner sidewall 121a of first semiconductor fin 111a faces and is adjacent to, but physically separated from, second inner sidewall 121b of second semiconductor fin 111b. Optionally, the semiconductor fins can further include one or more additional semiconductor fins 111c between and parallel to first semiconductor fin 111a and second semiconductor fin 111b (e.g., see semiconductor structure 100.6). For purposes of illustration only, one additional semiconductor fin is shown in
As illustrated, the first semiconductor fin 111a, the second semiconductor fin 111b, and, if applicable, any additional semiconductor fin 111c can be etched into the top surface of a bulk semiconductor substrate 102. This bulk semiconductor substrate 102 can be, for example, a monocrystalline silicon (Si) substrate or a bulk semiconductor substrate of any other suitable monocrystalline semiconductor material (e.g., silicon germanium (SiGe), germanium (Ge), etc.). In this case, an insulator layer 103 can be on substrate 102 laterally surrounding lower portions of the semiconductor fins with upper portions of the semiconductor fins extending above the level of the top surface of insulator layer 103. The effective fin height (h) of a semiconductor fin can correspond to the height of the upper portion, as measured from the top surface of the insulator layer 103 to the top surface of the semiconductor fin. Insulator layer 103 can, for example, be a silicon dioxide (SiO2) layer or a layer of any other suitable insulator material. Alternatively, the semiconductor fins can be etched into a semiconductor layer (e.g., a monocrystalline Si layer or a layer of some other suitable monocrystalline semiconductor material) of a semiconductor-on-insulator structure (e.g., a silicon-on-insulator (SOI) structure) or epitaxially grown within a mask.
Each semiconductor structure 100.1-100.6 can further include a multi-fin FINFET 110.1-110.6, each incorporating multiple semiconductor fins, as discussed above (or, more particularly, the upper portions thereof above the insulator layer 103). For purposes of illustration, FINFETs 110.1-110.5 of semiconductor structures 100.1-100.5 of
FINFET 110.1-110.6 can be an N-type FET (NFET) or a P-type FET (PFET). In any case, within the FINFET 110.1-110.6, first semiconductor fin 111a, second semiconductor fin 111b, and, if applicable, any additional semiconductor fin 111c can each further include a channel region positioned laterally between source/drain regions. Specifically, first semiconductor fin 111a can have a first channel region 112a positioned laterally between first source/drain regions 113a, second semiconductor fin 111b can have a second channel region 112b positioned laterally between second source/drain regions 113b, and, if applicable, each additional semiconductor fin 111c can have an additional channel region 112c positioned laterally between additional source/drain regions 113c. Various different source/drain configurations are known in the art and could be incorporated into FINFET 110.1-110.6. For example, the source/drain regions can include, for example, in situ doped epitaxial semiconductor material grown on the top surface and opposing sides of the semiconductor fins. The epitaxial semiconductor material on adjacent semiconductor fins can be physically separated such that each fin has discrete source/drain regions, as illustrated. Alternatively, the epitaxial semiconductor material on adjacent semiconductor fins can be merged so that the semiconductor fins have shared source/drain regions. Alternatively, the source/drain regions can have any other suitable source/drain region configuration known in the art. In any case, those skilled in the art will recognize that, typically, the channel regions of an NFET can be undoped (i.e., intrinsic) or, alternatively, doped so as to have P-type conductivity at a relatively low conductivity level (i.e., P-conductivity) and the source/drain regions can be doped so as to have N-type conductivity at a relatively high conductivity level (i.e., N+ conductivity or higher). The channel regions of a PFET can be undoped (i.e., intrinsic) or, alternatively, doped so as to have N-type conductivity at a relatively low conductivity level (i.e., N− conductivity) and the source/drain regions can be doped so as to have P-type conductivity at a relatively high conductivity level (i.e., P+ conductivity or higher).
Source/drain regions 113a, 113b, etc. can be covered with one or more middle of the line (MOL) dielectric layer(s) 195. Specifically, MOL dielectric layer(s) 195 can be on the top surface of the insulator layer 103 filling space around and between the semiconductor fins and source/drain regions and further extending over the source/drain regions. MOL dielectric layer(s) 195 can include, for example, an optional etch stop layer and a blanket interlayer dielectric (ILD) material layer on the etch stop layer. The optional etch stop layer can be, for example, a relatively thin conformal SiN layer or a relatively thin conformal layer of some other suitable etch stop material. The blanket ILD material layer can be, for example, a blanket layer of SiO2 layer, a doped silicon glass layer (e.g., phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG)), or a blanket layer of any other suitable ILD material.
FINFET 110.1-110.6 can further include a first isolation structure 180a (also referred to herein as a first gate cut isolation region) positioned laterally immediately adjacent to first outer sidewall 122a of first semiconductor fin 111a at first channel region 112a. As illustrated, first isolation structure 180a can, for example, be an essentially rectangular-shaped isolation structure including one or more layers of isolation material. The isolation material of first isolation structure 180a can include, for example, an oxide, such as SiO2 or a carbon-doped oxide dielectric (e.g., SiCOH), or some other suitable isolation material (e.g., SiON, etc.). In any case, the first isolation structure 180a can be taller than first semiconductor fin 111a, as measured from the top surface of insulator layer 103.
Optionally, the first semiconductor fin 111a can have a first groove 115a in first outer sidewall 122a at first channel region 112a. First groove 115a can extend from first top surface 123a of first semiconductor fin 111a downward (e.g., to the top surface of insulator layer 103). In some embodiments, as shown in FINFET 110.1 of semiconductor structure 100.1 of
In some embodiments, as shown in FINFET 110.1 of semiconductor structure 100.1 of
FINFET 110.1-110.6 can further include gate 163. Gate 163 can include a conformal gate dielectric layer 161, including one or more layers of gate dielectric material, and a gate conductor layer 162, including one or more layers of gate conductor material. Gate 163 can be, for example, a replacement metal gate (RMG). An RMG can include, for example: a high-K gate dielectric layer; a work function metal layer on the high-K gate dielectric layer; an optional doped polysilicon gate conductor layer on the work function metal layer; and an optional metal silicide layer on the doped polysilicon gate conductor layer. See the detailed discussion of RMG materials below. In any case, gate 163 can be positioned laterally immediately adjacent to first inner sidewall 121a of first semiconductor fin 111a opposite first isolation structure 180a and can further extend over first top surface 123a of first semiconductor fin 111a to first isolation structure 180a. Thus, a side of gate 163 and first semiconductor fin 111a have aligned surfaces in contact with an essentially vertical surface of first isolation structure 180a. For purposes of this disclosure, an essentially vertical surface refers to a surface that is approximately perpendicular to the bottom surface of the substrate (e.g., plus or minus 30 degrees from perpendicular). Gate 163 can further be immediately adjacent to at least second inner sidewall 121b and second top surface 123b of second semiconductor fin 111b. As mentioned above, in some embodiments (e.g., see FINFET 110.1 of semiconductor structure 100.1 of
FINFET 110.1-110.6 can further include gate sidewall spacers 199 laterally surrounding gate 163 and any isolation structure adjacent thereto (i.e., the first isolation structure 180a and, if applicable, the second isolation structure 180b). Gate sidewall spacers 199 can include one or more layers of dielectric sidewall spacer material (e.g., SiN, carbon-doped SiN, silicon boron carbon nitride (SiBCN) or any other suitable dielectric sidewall spacer material). Gate sidewall spacers 199 can electrically isolate gate 163 from the source/drain regions.
As mentioned above, a multi-fin FINFET will typically have semiconductor fins with the same dimensions and a Weff=Σ(2h+w)i, where h is the effective fin height (e.g., as measured from the top surface of the insulator layer 103), where w is top surface fin width at the channel region, and where i is the number of semiconductor fins. In other words, in a multi-fin FINFET the portion of Weff attributable to each semiconductor fin is typically essentially the same. In the disclosed embodiments, the portion of Weff attributable to first semiconductor fin 111a and, optionally, to second semiconductor fin 111b can be modified (e.g., fine-tuned) given placement of first isolation structure 180a and, optionally, a second isolation structure 180b. Specifically, first isolation structure 180a and, optionally, second isolation structure 180b can be placed so as to reduce the portion of Weff attributable to first semiconductor fin 111a and, optionally, second semiconductor fin 111b to at most h+w, where h is the effective fin height as measured from the top surface of insulator layer 103 and where w is the top surface fin width, as originally patterned. In some embodiments, it can be reduced to h+wr, where wr is a reduced fin width that is, for example, ˜½w.
The FINFETs 110.1-110.6 as described above and shown in the figures illustrate various different combinations of isolation structure placement that lead to different effective channel widths. For example, two-fin FINFET 110.1 in semiconductor structure 100.1 of FIGS. 1.1A-1.1C has a Weff=2*h+2*wr. In this case if wr˜½w, then Weff is essentially equal to that of a single-fin FINFET (i.e., 2*h+w). Two-fin FINFET 110.2 in semiconductor structure 100.2 of
Also disclosed herein are method embodiments for forming a semiconductor structure having a multi-fin FINFET with fine-tuned Weff, such as any of the semiconductor structures 100.1-100.6 described in detail above and illustrated in
The method can include forming multiple parallel semiconductor fins. The semiconductor fins can include a first semiconductor fin 111a, a second semiconductor fin 111b, and optionally one or more additional semiconductor fins (not shown) between and parallel to first semiconductor fin 111a and second semiconductor fin (see
A sacrificial gate structure 197 can be formed (see
Conventional sidewall spacer formation techniques can then be performed to form dielectric gate sidewall spacers 199 on the sidewalls of sacrificial gate structure 197. For example, a layer of dielectric sidewall spacer material (e.g., SiN, carbon-doped SiN, SiBCN or any other suitable dielectric sidewall spacer material) can be conformally deposited over the partially completed structure. The dielectric sidewall spacer material can then be anisotropically etched, removing it from essentially horizontal surfaces and leaving it intact, as sidewall spacers, on essentially vertical surfaces.
In situ doped epitaxial semiconductor material can be grown on exposed surfaces of semiconductor fins 111a, 111b, etc. on either side of sacrificial gate structure 197, thereby forming source/drain regions 113a, 113b, etc. (see
One or more MOL dielectric layer(s) 195 can be formed (e.g., deposited) over the partially completed semiconductor structure (see
In conventional FINFET processing, sacrificial gate structure 197 would then be selectively removed to form a gate opening and a gate (e.g., an RMG) would be formed within the gate opening such that it is on the opposing sides and top surface of each of the semiconductor fins at the designated channel regions therein. Contrarily, in the disclosed embodiments, prior to sacrificial gate structure removal, one or more isolation structures (also referred to herein as gate cut isolation structures) can be formed in sacrificial gate structure 197 (and partly into fin(s)) using conventional trench isolation formation techniques to selectively adjust the effective channel length of the resulting multi-fin FINFET.
For example, a mask layer 601 can be formed over the partially completed structure and one or more openings 602a-602b can be formed in mask layer 601 (e.g., using conventional lithographic processing and etch techniques) to expose one or more sections of sacrificial gate structure 197 within which the one or more isolation structures, respectively, are to be formed (see
Following formation of openings 602a, 602b, mask layer 601 can be removed and a first isolation structure 180a can be formed in the trench adjacent to the first outer sidewall of first semiconductor fin 111a (e.g., seated within first groove 115a) and a second isolation structure 180b can be formed in the trench adjacent to the second outer sidewall of second semiconductor fin 111b (e.g., seated within second groove 115b) (see
The remaining portion of sacrificial gate structure 197 can then be removed, creating a gate opening 902 (see
Gate 163 can be formed in gate opening 902 (e.g., see
Additional processing can include, but is not limited to, formation of one or more layers of ILD material over the FINFET, formation of contacts extending through the ILD material to FINFET components, formation of BEOL interconnects, etc. These features and techniques for forming them are well known in the art. Thus, the details thereof have been omitted from this specification in order to allow the reader to focus on the salient aspects of the disclosed embodiments.
It should be noted that in the structures and methods described above a semiconductor material refers to a material whose conducting properties can be altered by doping with an impurity. Such semiconductor materials include, for example, silicon-based semiconductor materials (e.g., silicon, silicon germanium, silicon germanium carbide, silicon carbide, etc.) and III-V compound semiconductors (i.e., compounds obtained by combining group III elements, such as aluminum (Al), gallium (Ga), or indium (In), with group V elements, such as nitrogen (N), phosphorous (P), arsenic (As) or antimony (Sb)) (e.g., GaN, InP, GaAs, or GaP). A pure semiconductor material and, more particularly, a semiconductor material that is not doped with an impurity for the purposes of increasing conductivity (i.e., an undoped semiconductor material) is referred to in the art as an intrinsic semiconductor. A semiconductor material that is doped with an impurity for the purposes of increasing conductivity (i.e., a doped semiconductor material) is referred to in the art as an extrinsic semiconductor and will be more conductive than an intrinsic semiconductor made of the same base material. That is, extrinsic silicon will be more conductive than intrinsic silicon; extrinsic silicon germanium will be more conductive than intrinsic silicon germanium; and so on. Furthermore, it should be understood that different impurities (i.e., different dopants) can be used to achieve different conductivity types (e.g., P-type conductivity and N-type conductivity) and that the dopants may vary depending upon the different semiconductor materials used. For example, a silicon-based semiconductor material (e.g., silicon, silicon germanium, etc.) is typically doped with a Group III dopant, such as boron (B) or indium (In), to achieve P-type conductivity, whereas a silicon-based semiconductor material is typically doped a Group V dopant, such as arsenic (As), phosphorous (P) or antimony (Sb), to achieve N-type conductivity. A gallium nitride (GaN)-based semiconductor material is typically doped with magnesium (Mg) to achieve P-type conductivity and with silicon (Si) or oxygen to achieve N-type conductivity. Those skilled in the art will also recognize that different conductivity levels will depend upon the relative concentration levels of the dopant(s) in a given semiconductor region. Furthermore, when a semiconductor region or layer is described as being at a higher conductivity level than another semiconductor region or layer, it is more conductive (less resistive) than the other semiconductor region or layer; whereas, when a semiconductor region or layer is described as being at a lower conductivity level than another semiconductor region or layer, it is less conductive (more resistive) than that other semiconductor region or layer.
It should further noted that in the structures and methods described above an RMG can include, for example: a high-K gate dielectric layer; a work function metal layer on the high-K gate dielectric layer; an optional doped polysilicon gate conductor layer on the work function metal layer; and an optional metal silicide layer on the doped polysilicon gate conductor layer. Various different RMG structures are known in the art and, thus, the details thereof have been omitted from this specification in order to allow the reader to focus on the salient aspects of the disclosed embodiments. However, those skilled in the art will recognize that the configuration of the gate stack for an RMG can vary depending upon whether the FET is an NFET or a PFET. For example, the optimal effective work function for the gate structure of an NFET is between about 3.9 eV and about 4.2 eV, whereas the optimal effective work function for the gate structure of a PFET is between about 4.9 eV and about 5.2 eV. In a gate-first polysilicon gate stack, the desired effective work function can be achieved, for example, by doping the polysilicon gate conductor layer with different dopants. For example, in an NFET, the polysilicon gate conductor layer can be doped with an N-type dopant (e.g., phosphorous (P), arsenic (As) or antimony (Sb)). In a PFET, the polysilicon gate conductor layer can be doped with P-type dopant (e.g., boron (B)). In a gate-first HKMG, the desired effective work function can be achieved, for example, using different metal layers on the high-K gate dielectric layer. For example, in an NFET, the metal layers on the high-K gate dielectric layer can include a titanium nitride (TiN) capping layer and, on the TiN capping layer, a lanthanum (La) layer for optimal NFET-specific dipole formation. In a PFET, the metal layers on the high-K gate dielectric layer can include a TiN capping layer and, on the TiN capping layer, an aluminum (Al) layer for optimal PFET-specific dipole formation. In an RMG, the desired effective work function can be achieved, for example, using different work function metal layers immediately adjacent to the high-K gate dielectric layer. Exemplary metals (and metal alloys), which have a work function within the range optimal for NFET performance (i.e., between 3.9 eV and about 4.2 eV) include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, and alloys thereof, such as, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. Exemplary metals (and metal alloys), which have a work function within the range optimal for PFET performance (i.e., between about 4.9 eV and about 5.2 eV) include, but are not limited to, ruthenium, palladium, platinum, cobalt, and nickel, as well as metal oxides (aluminum carbon oxide, aluminum titanium carbon oxide, etc.) and metal nitrides (e.g., titanium nitride, titanium silicon nitride, tantalum silicon nitride, titanium aluminum nitride, tantalum aluminum nitride, etc.). Such gate structures and the techniques for forming them are well known in the art and, thus, the details thereof have been omitted from this specification in order to allow the reader to focus on the salient aspects of the disclosed embodiments.
The method embodiments described above can be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
Additionally, in the structure and method embodiments described above, the terminology used is for the purpose of describing the disclosed structures and methods and is not intended to be limiting. For example, as used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Additionally, as used herein, the terms “comprises,” “comprising,” “includes” and/or “including” specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Furthermore, as used herein, terms such as “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” “upper,” “lower,” “under,” “below,” “underlying,” “over,” “overlying,” “parallel,” “perpendicular,” etc., are intended to describe relative locations as they are oriented and illustrated in the drawings (unless otherwise indicated) and terms such as “touching,” “in direct contact,” “abutting,” “directly adjacent to,” “immediately adjacent to,” etc., are intended to indicate that at least one element physically contacts another element (without other elements separating the described elements). The term “laterally” is used herein to describe the relative locations of elements and, more particularly, to indicate that an element is positioned to the side of another element as opposed to above or below the other element, as those elements are oriented and illustrated in the drawings. For example, an element that is positioned laterally adjacent to another element will be beside the other element, an element that is positioned laterally immediately adjacent to another element will be directly beside the other element, and an element that laterally surrounds another element will be adjacent to and border the outer sidewalls of the other element. The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed.
The descriptions of the various disclosed embodiments have been presented for purposes of illustration but are not intended to be exhaustive or limiting. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosed embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
