Neal Berger

Person

Cupertino, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory device comprising electrically floating body transistor
- Patent number 12,094,526
- Issue date Sep 17, 2024
- Zeno Semiconductor, Inc.
- Jin-Woo Han
- G11 - INFORMATION STORAGE
Information Patent Grant
MRAM access coordination systems and methods via pipeline in parallel
- Patent number 11,941,299
- Issue date Mar 26, 2024
- Integrated Silicon Solution, (Cayman) Inc.
- Benjamin Louie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device comprising electrically floating body transistor
- Patent number 11,715,515
- Issue date Aug 1, 2023
- Zeno Semiconductor, Inc.
- Jin-Woo Han
- G11 - INFORMATION STORAGE
Information Patent Grant
Error cache system with coarse and fine segments for power optimiza...
- Patent number 11,586,553
- Issue date Feb 21, 2023
- Integrated Silicon Solution, (Cayman) Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Heuristics for selecting subsegments for entry in and entry out ope...
- Patent number 11,580,014
- Issue date Feb 14, 2023
- Integrated Silicon Solution, (Cayman) Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Word line decoder memory architecture
- Patent number 11,423,965
- Issue date Aug 23, 2022
- Integrated Silicon Solution, (Cayman) Inc.
- Neal Berger
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit engine for managing memory meta-stability
- Patent number 11,386,010
- Issue date Jul 12, 2022
- Integrated Silicon Solution, (Cayman) Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
MRAM access coordination systems and methods with a plurality of pi...
- Patent number 11,334,288
- Issue date May 17, 2022
- Integrated Silicon Solution, (Cayman) Inc.
- Benjamin Louie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device comprising electrically floating body transistor
- Patent number 11,250,905
- Issue date Feb 15, 2022
- Zeno Semiconductor, Inc.
- Jin-Woo Han
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Error cache segmentation for power reduction
- Patent number 11,151,042
- Issue date Oct 19, 2021
- Integrated Silicon Solution, (Cayman) Inc.
- Benjamin Louie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Heuristics for selecting subsegments for entry in and entry out ope...
- Patent number 11,119,910
- Issue date Sep 14, 2021
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error cache system with coarse and fine segments for power optimiza...
- Patent number 11,119,936
- Issue date Sep 14, 2021
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Determining an inactive memory bank during an idle memory cycle to...
- Patent number 11,048,633
- Issue date Jun 29, 2021
- Spin Memory, Inc.
- Susmita Karmakar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
MRAM noise mitigation for write operations with simultaneous backgr...
- Patent number 11,010,294
- Issue date May 18, 2021
- Spin Memory, Inc.
- Benjamin Louie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
MRAM noise mitigation for background operations by delaying verify...
- Patent number 10,990,465
- Issue date Apr 27, 2021
- Spin Memory, Inc.
- Benjamin Louie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bi-polar write scheme
- Patent number 10,991,410
- Issue date Apr 27, 2021
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory array with individually trimmable sense amplifiers
- Patent number 10,930,332
- Issue date Feb 23, 2021
- Spin Memory, Inc.
- Susmita Karmakar
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device comprising electrically floating body transistor
- Patent number 10,923,183
- Issue date Feb 16, 2021
- Zeno Semiconductor, Inc.
- Jin-Woo Han
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array with horizontal source line and a virtual source line
- Patent number 10,891,997
- Issue date Jan 12, 2021
- Spin Memory, Inc.
- Neal Berger
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-chip module for MRAM devices with levels of dynamic redundanc...
- Patent number 10,818,331
- Issue date Oct 27, 2020
- Spin Memory, Inc.
- Benjamin Louie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Master slave level shift latch for word line decoder memory archite...
- Patent number 10,803,949
- Issue date Oct 13, 2020
- Spin Memory, Inc.
- Neal Berger
- G11 - INFORMATION STORAGE
Information Patent Grant
Word line decoder memory architecture
- Patent number 10,699,761
- Issue date Jun 30, 2020
- Spin Memory, Inc.
- Neal Berger
- G11 - INFORMATION STORAGE
Information Patent Grant
Over-voltage write operation of tunnel magnet-resistance (“TMR”) me...
- Patent number 10,656,994
- Issue date May 19, 2020
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with a plurality of memory banks where each memory ba...
- Patent number 10,628,316
- Issue date Apr 21, 2020
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device comprising electrically floating body transistor
- Patent number 10,580,482
- Issue date Mar 3, 2020
- Zeno Semiconductor, Inc.
- Jin-Woo Han
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-port random access memory
- Patent number 10,546,624
- Issue date Jan 28, 2020
- Spin Memory, Inc.
- Mourad El Baraji
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of optimizing write voltage based on error buffer occupancy
- Patent number 10,546,625
- Issue date Jan 28, 2020
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-the-fly bit failure detection and bit redundancy remapping techn...
- Patent number 10,529,439
- Issue date Jan 7, 2020
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Forcing stuck bits, waterfall bits, shunt bits and low TMR bits to...
- Patent number 10,489,245
- Issue date Nov 26, 2019
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Forcing bits as bad to widen the window between the distributions o...
- Patent number 10,481,976
- Issue date Nov 19, 2019
- Spin Memory, Inc.
- Neal Berger
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Memory Device Comprising Electrically Floating Body Transistor
- Publication number 20240404585
- Publication date Dec 5, 2024
- Zeno Semiconductor, Inc.
- Jin-Woo Han
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE COMPRISING ELECTRICALLY FLOATING BODY TRANSISTOR
- Publication number 20230326516
- Publication date Oct 12, 2023
- Zeno Semiconductor, Inc.
- Jin-Woo Han
- G11 - INFORMATION STORAGE
Information Patent Application
MRAM ACCESS COORDINATION SYSTEMS AND METHODS
- Publication number 20220276807
- Publication date Sep 1, 2022
- Integrated Silicon Solution, (Cayman) Inc.
- Benjamin LOUIE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE COMPRISING ELECTRICALLY FLOATING BODY TRANSISTOR
- Publication number 20220130451
- Publication date Apr 28, 2022
- Zeno Semiconductor, Inc.
- Jin-Woo Han
- G11 - INFORMATION STORAGE
Information Patent Application
ERROR CACHE SYSTEM WITH COARSE AND FINE SEGMENTS FOR POWER OPTIMIZA...
- Publication number 20220107900
- Publication date Apr 7, 2022
- Integrated Silicon Solution, (Cayman) Inc.
- Neal BERGER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HEURISTICS FOR SELECTING SUBSEGMENTS FOR ENTRY IN AND ENTRY OUT OPE...
- Publication number 20220107888
- Publication date Apr 7, 2022
- Integrated Silicon Solution, (Cayman) Inc.
- Neal BERGER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE COMPRISING ELECTRICALLY FLOATING BODY TRANSISTOR
- Publication number 20210183432
- Publication date Jun 17, 2021
- Zeno Semiconductor, Inc.
- Jin-Woo Han
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CIRCUIT ENGINE FOR MANAGING MEMORY META-STABILITY
- Publication number 20210089455
- Publication date Mar 25, 2021
- Spin Memory, Inc.
- Neal BERGER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Master Slave Level Shift Latch for Word Line Decoder Memory Archite...
- Publication number 20200286561
- Publication date Sep 10, 2020
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
WORD LINE DECODER MEMORY ARCHITECTURE
- Publication number 20200227102
- Publication date Jul 16, 2020
- Spin Memory, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE COMPRISING ELECTRICALLY FLOATING BODY TRANSISTOR
- Publication number 20200168267
- Publication date May 28, 2020
- Zeno Semiconductor, Inc.
- Jin-Woo Han
- G11 - INFORMATION STORAGE
Information Patent Application
ERROR CACHE SYSTEM WITH COARSE AND FINE SEGMENTS FOR POWER OPTIMIZA...
- Publication number 20200117610
- Publication date Apr 16, 2020
- Spin Memory, Inc.
- Neal BERGER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HEURISTICS FOR SELECTING SUBSEGMENTS FOR ENTRY IN AND ENTRY OUT OPE...
- Publication number 20200117592
- Publication date Apr 16, 2020
- Spin Memory, Inc.
- Neal BERGER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WORD LINE DECODER MEMORY ARCHITECTURE
- Publication number 20200090721
- Publication date Mar 19, 2020
- Spin Memory, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
MRAM NOISE MITIGATION FOR BACKGROUND OPERATIONS BY DELAYING VERIFY...
- Publication number 20200057687
- Publication date Feb 20, 2020
- Spin Memory, Inc.
- Benjamin LOUIE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MRAM NOISE MITIGATION FOR WRITE OPERATIONS WITH SIMULTANEOUS BACKGR...
- Publication number 20200050545
- Publication date Feb 13, 2020
- Spin Memory, Inc.
- Benjamin LOUIE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DETERMINING AN INACTIVE MEMORY BANK DURING AN IDLE MEMORY CYCLE TO...
- Publication number 20200042451
- Publication date Feb 6, 2020
- Spin Memory, Inc.
- Susmita KARMAKAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR CACHE SEGMENTATION FOR POWER REDUCTION
- Publication number 20200042450
- Publication date Feb 6, 2020
- Spin Memory, Inc.
- Benjamin LOUIE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BI-POLAR WRITE SCHEME
- Publication number 20200043540
- Publication date Feb 6, 2020
- Spin Memory, Inc.
- Neal BERGER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ARRAY WITH INDIVIDUALLY TRIMMABLE SENSE AMPLIFIERS
- Publication number 20190348097
- Publication date Nov 14, 2019
- Spin Memory, Inc.
- Susmita KARMAKAR
- G11 - INFORMATION STORAGE
Information Patent Application
MRAM ACCESS COORDINATION SYSTEMS AND METHODS
- Publication number 20190303044
- Publication date Oct 3, 2019
- Spin Memory, Inc.
- Benjamin LOUIE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERPENDICULAR SOURCE AND BIT LINES FOR AN MRAM ARRAY
- Publication number 20190206470
- Publication date Jul 4, 2019
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-PORT RANDOM ACCESS MEMORY
- Publication number 20190206468
- Publication date Jul 4, 2019
- Spin Transfer Technologies, Inc.
- Mourad EL-BARAJI
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARRAY WITH INDIVIDUALLY TRIMMABLE SENSE AMPLIFIERS
- Publication number 20190206467
- Publication date Jul 4, 2019
- Spin Transfer Technologies, Inc.
- Susmita KARMAKAR
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARRAY WITH HORIZONTAL SOURCE LINE AND SACRIFICIAL BITLINE PE...
- Publication number 20190206473
- Publication date Jul 4, 2019
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY ARRAY WITH HORIZONTAL SOURCE LINE AND A VIRTUAL SOURCE LINE
- Publication number 20190206471
- Publication date Jul 4, 2019
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-CHIP MODULE FOR MRAM DEVICES
- Publication number 20190180807
- Publication date Jun 13, 2019
- Spin Transfer Technologies, Inc.
- Benjamin LOUIE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF OPTIMIZING WRITE VOLTAGE BASED ON ERROR BUFFER OCCUPANCY
- Publication number 20190139590
- Publication date May 9, 2019
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-THE-FLY BIT FAILURE DETECTION AND BIT REDUNDANCY REMAPPING TECHN...
- Publication number 20190122746
- Publication date Apr 25, 2019
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE
Information Patent Application
OVER-VOLTAGE WRITE OPERATION OF TUNNEL MAGNET-RESISTANCE ("TMR") ME...
- Publication number 20190121694
- Publication date Apr 25, 2019
- Spin Transfer Technologies, Inc.
- Neal BERGER
- G11 - INFORMATION STORAGE

Neal Berger

Person

Patents Grantslast 30 patents

Memory device comprising electrically floating body transistor

MRAM access coordination systems and methods via pipeline in parallel

Memory device comprising electrically floating body transistor

Error cache system with coarse and fine segments for power optimiza...

Heuristics for selecting subsegments for entry in and entry out ope...

Word line decoder memory architecture

Circuit engine for managing memory meta-stability

MRAM access coordination systems and methods with a plurality of pi...

Memory device comprising electrically floating body transistor

Error cache segmentation for power reduction

Heuristics for selecting subsegments for entry in and entry out ope...

Error cache system with coarse and fine segments for power optimiza...

Determining an inactive memory bank during an idle memory cycle to...

MRAM noise mitigation for write operations with simultaneous backgr...

MRAM noise mitigation for background operations by delaying verify...

Bi-polar write scheme

Memory array with individually trimmable sense amplifiers

Memory device comprising electrically floating body transistor

Memory array with horizontal source line and a virtual source line

Multi-chip module for MRAM devices with levels of dynamic redundanc...

Master slave level shift latch for word line decoder memory archite...

Word line decoder memory architecture

Over-voltage write operation of tunnel magnet-resistance (“TMR”) me...

Memory device with a plurality of memory banks where each memory ba...

Memory device comprising electrically floating body transistor

Multi-port random access memory

Method of optimizing write voltage based on error buffer occupancy

On-the-fly bit failure detection and bit redundancy remapping techn...

Forcing stuck bits, waterfall bits, shunt bits and low TMR bits to...

Forcing bits as bad to widen the window between the distributions o...

Patents Applicationslast 30 patents

Memory Device Comprising Electrically Floating Body Transistor

MEMORY DEVICE COMPRISING ELECTRICALLY FLOATING BODY TRANSISTOR

MRAM ACCESS COORDINATION SYSTEMS AND METHODS

MEMORY DEVICE COMPRISING ELECTRICALLY FLOATING BODY TRANSISTOR

ERROR CACHE SYSTEM WITH COARSE AND FINE SEGMENTS FOR POWER OPTIMIZA...

HEURISTICS FOR SELECTING SUBSEGMENTS FOR ENTRY IN AND ENTRY OUT OPE...

MEMORY DEVICE COMPRISING ELECTRICALLY FLOATING BODY TRANSISTOR

CIRCUIT ENGINE FOR MANAGING MEMORY META-STABILITY

Master Slave Level Shift Latch for Word Line Decoder Memory Archite...

WORD LINE DECODER MEMORY ARCHITECTURE

MEMORY DEVICE COMPRISING ELECTRICALLY FLOATING BODY TRANSISTOR

ERROR CACHE SYSTEM WITH COARSE AND FINE SEGMENTS FOR POWER OPTIMIZA...

HEURISTICS FOR SELECTING SUBSEGMENTS FOR ENTRY IN AND ENTRY OUT OPE...

WORD LINE DECODER MEMORY ARCHITECTURE

MRAM NOISE MITIGATION FOR BACKGROUND OPERATIONS BY DELAYING VERIFY...

MRAM NOISE MITIGATION FOR WRITE OPERATIONS WITH SIMULTANEOUS BACKGR...

DETERMINING AN INACTIVE MEMORY BANK DURING AN IDLE MEMORY CYCLE TO...

ERROR CACHE SEGMENTATION FOR POWER REDUCTION

BI-POLAR WRITE SCHEME

MEMORY ARRAY WITH INDIVIDUALLY TRIMMABLE SENSE AMPLIFIERS

MRAM ACCESS COORDINATION SYSTEMS AND METHODS

PERPENDICULAR SOURCE AND BIT LINES FOR AN MRAM ARRAY

MULTI-PORT RANDOM ACCESS MEMORY

MEMORY ARRAY WITH INDIVIDUALLY TRIMMABLE SENSE AMPLIFIERS

MEMORY ARRAY WITH HORIZONTAL SOURCE LINE AND SACRIFICIAL BITLINE PE...

MEMORY ARRAY WITH HORIZONTAL SOURCE LINE AND A VIRTUAL SOURCE LINE

MULTI-CHIP MODULE FOR MRAM DEVICES

METHOD OF OPTIMIZING WRITE VOLTAGE BASED ON ERROR BUFFER OCCUPANCY

ON-THE-FLY BIT FAILURE DETECTION AND BIT REDUNDANCY REMAPPING TECHN...

OVER-VOLTAGE WRITE OPERATION OF TUNNEL MAGNET-RESISTANCE ("TMR") ME...