Memory device comprising electrically floating body transistor

Description

FIELD OF THE INVENTION

The present invention relates to semiconductor memory technology. More specifically, the present invention relates to a semiconductor memory device comprising an electrically floating body transistor.

BACKGROUND OF THE INVENTION

Semiconductor memory devices are used extensively to store data. Memory devices can be characterized according to two general types: volatile and non-volatile. Volatile memory devices such as static random access memory (SRAM) and dynamic random access memory (DRAM) lose data that is stored therein when power is not continuously supplied thereto.

A DRAM cell without a capacitor has been investigated previously. Such memory eliminates the capacitor used in the conventional 1T/1C memory cell, and thus is easier to scale to smaller feature size. In addition, such memory allows for a smaller cell size compared to the conventional 1T/1C memory cell. Chatterjee et al. have proposed a Taper Isolated DRAM cell concept in “Taper Isolated Dynamic Gain RAM Cell”, P. K. Chatterjee et al., pp. 698-699, International Electron Devices Meeting, 1978 (“Chatterjee-1”), “Circuit Optimization of the Taper Isolated Dynamic Gain RAM Cell for VLSI Memories”, P. K. Chatterjee et al., pp. 22-23, IEEE International Solid-State Circuits Conference, February 1979 (“Chatterjee-2”), and “dRAM Design Using the Taper-Isolated Dynamic RAM Cell”, J. E. Leiss et al., pp. 337-344, IEEE Journal of Solid-State Circuits, vol. SC-17, no. 2, April 1982 (“Leiss”), all of which are hereby incorporated herein, in their entireties, by reference thereto. The holes are stored in a local potential minimum, which looks like a bowling alley, where a potential barrier for stored holes is provided. The channel region of the Taper Isolated DRAM cell contains a deep n-type implant and a shallow p-type implant. As shown in “A Survey of High-Density Dynamic RAM Cell Concepts”, P. K. Chatterjee et al., pp. 827-839, IEEE Transactions on Electron Devices, vol. ED-26, no. 6, June 1979 (“Chatterjee-3”), which is hereby incorporated herein, in its entirety, by reference thereto, the deep n-type implant isolates the shallow p-type implant and connects the n-type source and drain regions.

Terada et al. have proposed a Capacitance Coupling (CC) cell in “A New VLSI Memory Cell Using Capacitance Coupling (CC) Cell”, K. Terada et al., pp. 1319-1324, IEEE Transactions on Electron Devices, vol. ED-31, no. 9, September 1984 (“Terada”), while Erb has proposed Stratified Charge Memory in “Stratified Charge Memory”, D. M. Erb, pp. 24-25, IEEE International Solid-State Circuits Conference, February 1978 (“Erb”), both of which are hereby incorporated herein, in their entireties, by reference thereto.

DRAM based on the electrically floating body effect has been proposed both in silicon-on-insulator (SOI) substrate (see for example “The Multistable Charge-Controlled Memory Effect in SOI Transistors at Low Temperatures”, Tack et al., pp. 1373-1382, IEEE Transactions on Electron Devices, vol. 37, May 1990 (“Tack”), “A Capacitor-less 1T-DRAM Cell”, S. Okhonin et al., pp. 85-87, IEEE Electron Device Letters, vol. 23, no. 2, February 2002 and “Memory Design Using One-Transistor Gain Cell on SOI”, T. Ohsawa et al., pp. 152-153, Tech. Digest, 2002 IEEE International Solid-State Circuits Conference, February 2002, (all of which are hereby incorporated herein, in their entireties, by reference thereto) and in bulk silicon (see for example “A one transistor cell on bulk substrate (1T-Bulk) for low-cost and high density eDRAM”, R. Ranica et al., pp. 128-129, Digest of Technical Papers, 2004 Symposium on VLSI Technology, June 2004 (“Ranica-1”), “Scaled 1T-Bulk Devices Built with CMOS 90 nm Technology for Low-Cost eDRAM Applications”, R. Ranica et al., 2005 Symposium on VLSI Technology, Digest of Technical Papers (“Ranica-2”), “Further Insight Into the Physics and Modeling of Floating-Body Capacitorless DRAMs”, A. Villaret et al, pp. 2447-2454, IEEE Transactions on Electron Devices, vol. 52, no. 11, November 2005 (“Villaret”), “Simulation of intrinsic bipolar transistor mechanisms for future capacitor-less eDRAM on bulk substrate”, R. Pulicani et al., pp. 966-969, 2010 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS) (“Pulicani”), which are hereby incorporated herein, in their entireties, by reference thereto).

Widjaja and Or-Bach describes a bi-stable SRAM cell incorporating a floating body transistor, where more than one stable state exists for each memory cell (for example as described in U.S. Pat. No. 8,130,548 to Widjaja et al., titled “Semiconductor Memory Having Floating Body Transistor and Method of Operating” (“Widjaja-1”), U.S. Pat. No. 8,077,536, “Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle” (“Widjaja-2”), U.S. Patent Application Publication No. 2013/0264656 A113/746,523, “Memory Device Having Electrically Floating Body Transistor” (“Widjaja-3”), all of which are hereby incorporated herein, in their entireties, by reference thereto). This bi-stability is achieved due to the applied back bias which causes impact ionization and generates holes to compensate for the charge leakage current and recombination.

SUMMARY OF THE INVENTION

A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.

In one aspect of the present invention, a semiconductor memory instance is provided that includes an array of memory cells, including a plurality of semiconductor memory cells arranged in at least one column and at least one row. Each semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a plurality of buried well regions, wherein each of the buried well regions can be individually selected; and a decoder circuit to select at least one of the buried well regions.

In at least one embodiment, each memory cell is configured to provide at least two stable states.

In at least one embodiment, each memory cell further comprises a first region in electrical contact with the floating body region and a second region in electrical contact with the floating body region.

In at least one embodiment, each memory cell further comprises a gate positioned between the first and second regions.

In at least one embodiment, an address signal is provided as an input to the decoder circuit to select the buried well region.

In at least one embodiment, a bias to one or more of the buried well regions may be removed, while maintaining bias to others of the buried well regions.

In at least one embodiment, a signal generator circuit is provided to supply bias conditions for operations of the array.

In at least one embodiment, the signal generator circuit provides different ramp rates for read and write operations.

In at least one embodiment, the ramp rates for the read operations are lower than the ramp rates for the write operations.

In another aspect of the present invention, a semiconductor memory instance includes: an array of semiconductor memory cells, the array comprising at least one memory sub-array, each memory sub-array comprising: a plurality of the semiconductor memory cells arranged in at least one column and at least one row, each the semiconductor memory cell comprising: a floating body region configured to be charged to a level indicative of a state of the semiconductor memory cell; a buried well region; and a decoder circuit to select at least one of the at least one memory sub-array.

In at least one embodiment, at least one of the at least one memory sub-array may be selectively disabled.

In at least one embodiment, a bias to the buried well region within one of the at least one memory sub-array may be applied to maintain the states of the semiconductor memory cells in the one of the at least one memory sub-array during a high portion of a clock cycle and turned-off during a low portion of the clock cycle.

In at least one embodiment, each semiconductor memory cell is configured to provide at least two stable states.

In another aspect of the present invention, an integrated circuit device includes an array of semiconductor memory cells, the array comprising: a plurality of the semiconductor memory cells arranged in at least one column and at least one row, each semiconductor memory cell comprising: a floating body region configured to be charged to a level indicative of a state of the semiconductor memory cell, respectively; a plurality of buried well regions, wherein each buried well region can be individually selected; and a decoder circuit to select at least one of the buried well regions.

In at least one embodiment, the integrated circuit device further includes a supply generator circuitry.

In at least one embodiment, each semiconductor memory cell is configured to provide at least two stable states.

In at least one embodiment, the integrated circuit device further includes an address signal as an input to the decoder circuit to select at least one of the buried well regions.

In at least one embodiment, a bias to at least one of the buried well regions may be removed, while maintaining bias to at least one other of the buried well regions.

In at least one embodiment, the integrated circuit device further includes a signal generator circuit to provide bias conditions for operations of the array.

In at least one embodiment, the signal generator circuit provides different ramp rates for read and write operations.

These and other features of the invention will become apparent to those persons skilled in the art upon reading the details of the devices and methods as more fully described below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a block diagram for a memory instance according to an embodiment of the present invention.

FIG. 1B is a schematic layout view of a prior art 6-transistor SRAM memory cell.

FIG. 1C schematically illustrates a layout view of a memory array according to an embodiment of the present invention.

FIGS. 2 and 3 schematically illustrate cross-sectional views of a memory cell according to an embodiment of the present invention.

FIG. 4A is a schematic, cross-sectional illustration of a memory cell according to another embodiment of the present invention.

FIG. 4B is a schematic, top-view illustration of the memory cell shown in FIG. 4A.

FIGS. 4C and 4D schematically illustrate a layout view of a memory array according to an embodiment of the present invention.

FIGS. 5 and 6 schematically illustrate equivalent circuit representations of the memory cells shown in FIGS. 2-4.

FIG. 7 schematically illustrates multiple cells of the type shown in FIGS. 2-4 joined to make a memory array, according to an embodiment of the present invention.

FIG. 8A schematically illustrates a holding operation performed on a memory array according to an embodiment of the present invention.

FIG. 8B illustrates exemplary bias conditions applied on the terminals of a memory cell of the array of FIG. 8A.

FIG. 9A shows an energy band diagram characterizing an intrinsic bipolar device when a floating body region is positively charged and a positive bias is applied to a buried well region of a memory cell according to an embodiment of the present invention.

FIG. 9B shows an energy band diagram of an intrinsic bipolar device when a floating body region is neutrally charged and a positive bias is applied to a buried well region of a memory cell according to an embodiment of the present invention.

FIG. 10 shows a graph of the net current I flowing into or out of a floating body region as a function of the potential V of the floating body, according to an embodiment of the present invention.

FIG. 11 shows a schematic curve of a potential energy surface (PES) of a memory cell according to an embodiment of the present invention.

FIG. 12 illustrates a charge stored in a floating body region of a memory cell as a function of a potential applied to a buried well region, connected to a BW terminal, according to an embodiment of the present invention.

FIG. 13A illustrates memory array segmentation with multiple memory sub-arrays. The BW terminals may be controlled independently for each memory sub-array according to an embodiment of the present invention.

FIG. 13B illustrates an exemplary BW terminal decoder circuitry, according to an embodiment of the present invention.

FIG. 14 schematically illustrates a read operation performed on a memory array according to an embodiment of the present invention.

FIG. 15 illustrates bias conditions applied on the terminals of a selected memory cell to perform a read operation, according to an embodiment of the present invention.

FIG. 16 schematically illustrate an equivalent capacitor circuit representation of the memory cells shown in FIGS. 2-4.

FIG. 17 shows a schematic map of word line voltage and bit line voltage that enables a floating body potential to be higher than a transition voltage for write logic-1, according to an embodiment of the present invention.

FIGS. 18A and 18B schematically illustrate a write logic-1 operation performed on a memory array according to an embodiment of the present invention.

FIGS. 19A and 19B schematically illustrate a write logic-1 operation performed on a memory array according to another embodiment of the present invention.

FIG. 20 shows a schematic map of word line voltage and bit line voltage that enables a floating body potential to be lower than a transition voltage for write logic-0, according to an embodiment of the present invention.

FIG. 21 schematically illustrates a write logic-0 operation performed on a memory array according to an embodiment of the present invention.

FIG. 22 illustrates bias conditions applied on the terminals of a selected memory cell to perform a write logic-0 operation, according to an embodiment of the present invention.

FIG. 23 schematically illustrates a write logic-0 operation performed on a memory array according to another embodiment of the present invention.

FIG. 24 illustrates bias conditions applied on the terminals of a selected memory cell to perform a write logic-0 operation according to another embodiment of the present invention.

FIG. 25 schematically illustrates a write logic-0 operation performed on a memory array according to another embodiment of the present invention.

FIG. 26 illustrates bias conditions applied on the terminals of a selected memory cell to perform a write logic-0 operation according to another embodiment of the present invention.

FIG. 27 shows a schematic map of word line voltage and bit line voltage for holding logic-1 states, according to an embodiment of the present invention.

FIG. 28 schematically illustrates a holding operation performed on a memory array according to another embodiment of the present invention.

FIGS. 29A and 29B are schematic, top-view illustrations of the memory cell shown in FIGS. 2-4 having increased capacitive coupling from source/drain regions to the floating body region.

FIG. 30 schematically illustrates a layout view of a memory cell according to another embodiment of the present invention.

FIGS. 31-34 schematically illustrate lithography steps to form the memory cell shown in FIGS. 1C and 2-4 according an embodiment of the present invention.

FIGS. 35-37 schematically illustrate multiple cells of the type in FIGS. 2-4 joined in an array according to another embodiment of the present invention.

FIG. 38 schematically illustrates a read operation performed on the memory array shown in FIGS. 35-37 according to an embodiment of the present invention.

FIGS. 39-40 schematically illustrate self-reference read operation scheme according to an embodiment of the present invention.

FIGS. 41-42 are schematic, cross-sectional illustrations of a vertical channel memory cell according to another embodiment of the present invention.

FIG. 43 illustrates an equivalent circuit representation of the memory cell shown in FIGS. 41-42.

FIG. 44 illustrates bias conditions applied on the terminals of a memory cell to perform a holding operation, according to an embodiment of the present invention.

FIG. 45A shows an energy band diagram characterizing an intrinsic bipolar device when a floating body region is positively charged and a positive bias is applied to a buried well region of a memory cell according to an embodiment of the present invention.

FIG. 45B shows an energy band diagram of an intrinsic bipolar device when a floating body region is neutrally charged and a positive bias is applied to a buried well region of a memory cell according to an embodiment of the present invention.

FIG. 46 illustrates bias conditions applied on the terminals of a memory cell to perform a read operation, according to an embodiment of the present invention.

FIGS. 47 and 48 illustrate bias conditions applied on the terminals of a memory cell to perform a write logic-1 operation, according to an embodiment of the present invention.

FIGS. 49 and 50 illustrate bias conditions applied on the terminals of a memory cell to perform a write logic-0 operation, according to an embodiment of the present invention.

FIG. 51 is a schematic, top-view illustration of a multi-time programmable (MTP) memory cell according to another embodiment of the present invention.

FIGS. 52A-52B are schematic, cross-sectional illustrations of an MTP memory cell shown in FIG. 51.

FIG. 52C illustrates an equivalent circuit representation of a memory cell of FIGS. 52A-52B.

DETAILED DESCRIPTION OF THE INVENTION

Before the present devices and methods are described, it is to be understood that this invention is not limited to particular embodiments described, as such may, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting, since the scope of the present invention will be limited only by the appended claims.

Where a range of values is provided, it is understood that each intervening value, to the tenth of the unit of the lower limit unless the context clearly dictates otherwise, between the upper and lower limits of that range is also specifically disclosed. Each smaller range between any stated value or intervening value in a stated range and any other stated or intervening value in that stated range is encompassed within the invention. The upper and lower limits of these smaller ranges may independently be included or excluded in the range, and each range where either, neither or both limits are included in the smaller ranges is also encompassed within the invention, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included in the invention.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Although any methods and materials similar or equivalent to those described herein can be used in the practice or testing of the present invention, the preferred methods and materials are now described. All publications mentioned herein are incorporated herein by reference to disclose and describe the methods and/or materials in connection with which the publications are cited.

It must be noted that as used herein and in the appended claims, the singular forms “a”, “an”, and “the” include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to “a terminal” includes a plurality of such terminals and reference to “the cell” includes reference to one or more cells and equivalents thereof known to those skilled in the art, and so forth.

The publications discussed herein are provided solely for their disclosure prior to the filing date of the present application. The dates of publication provided may be different from the actual publication dates which may need to be independently confirmed.

FIG. 1A illustrates a memory instance 1200, comprising memory array 100 and periphery circuitries associated with the memory array 100. Examples of the periphery circuitries are shown in FIG. 1A: control logic 102 which receives for example enable (/E) and write (/W) signals and controls the operation of the memory array; address buffer 110, which transmits the address received to row decoder 112 and column decoder 114; reading circuitry such as sense amplifier 116 and error correction circuit (ECC) 118; data buffer 120, which outputs the read data or transmits the write data into write drivers 125; analog supply generators and/or regulators 135 which provide additional voltage levels needed for the memory array operation; redundancy logic 145 which may be used to increase the yield of the memory instance; built-in-self-test (BIST) 155 which may be used to set the trim levels for the supply generators 135 and/or replace the defective units with redundant array. The memory instance 1200 may be a discrete memory component or it may be embedded inside another integrated circuit device 1000.

FIG. 1B is a layout view of a six-transistor SRAM cell 2000 (for example as described in “Embedded Memories for Nano-Scale VLSI, K. Zhang (ed.), p. 42). The SRAM unit cell (the basic repeating cell) 2002 is shown inside the dashed line. The SRAM unit cell 2002 comprises 4 n-type transistors 2004 and 2 p-type transistors 2006. The transistors 2004, 2006 are defined by the DIFF layer and the POLY gate. The DIFF layer represents the active area of the transistor (which typically covers the channel region and the source and drain junctions) while the POLY layer represents the region of the materials forming the gate electrode. The area where DIFF and POLY intersects defines the channel region as well as the gate region of the transistors. The POLY layers defining the n-type transistors are labeled as N1, N4, N5, and N6, while the POLY layers defining the p-type transistors are labeled as P1 and P2. As the example in FIG. 1B illustrates, the transistor width (defined by the width of the DIFF layer) varies between the n-type and p-type transistors. The width of the n-type transistors may also be different in another SRAM design to improve the stability and performance of the SRAM cell.

FIG. 1C illustrates a layout view of an exemplary memory array 100 according to an embodiment of the present invention. The exemplary memory array 100 in FIG. 1C comprises two rows and two columns, where one direction (for example the row direction) is defined by the POLY layers 160 and another direction (for example the column direction) is defined by the long direction of the DIFF layers 130 (or the METAL2 layers 146 in FIG. 4D). There are four memory cells 50 shown in FIG. 1C and the unit cell (the basic repeating cell) is enclosed in dashed lines. Also shown in the layout view of FIG. 1C are CONTACT layer 140, source and drain regions 16 and 18, and floating body region 24 as well as buried well layer 170.

Referring to FIG. 2, a memory cell 50 according to an embodiment of the present invention is shown. A plurality of memory cells 50 constitute memory array 100 as shown in FIG. 1C. Memory cell 50 includes a substrate 12 of a first conductivity type such as p-type, for example. Alternatively, the first conductivity type can be n-type. Substrate 12 is typically made of silicon, but may also comprise, for example, germanium, silicon germanium, gallium arsenide, carbon nanotubes, and/or other semiconductor materials. In some embodiments of the invention, substrate 12 can be the bulk material of the semiconductor wafer. In another embodiment shown in FIG. 3, substrate 12A of a first conductivity type (for example, p-type) can be a well of the first conductivity type embedded in a well 29 of the second conductivity type, such as n-type. The well 29 in turn can be another well inside substrate 12B of the first conductivity type (for example, p-type). In another embodiment, well 12A can be embedded inside the bulk of the semiconductor wafer of the second conductivity type (for example, n-type), where region 29 represents bulk semiconductor substrate having second conductivity type. These arrangements allow for segmentation of the substrate terminal, which is connected to region 12A. To simplify the description, the substrate 12 will usually be drawn as the semiconductor bulk material as it is in FIG. 2.

Memory cell 50 also includes a buried layer region 22 of a second conductivity type, such as n-type, for example (or p-type, when the first conductivity type is n-type); a floating body region 24 of the first conductivity type, such as p-type, for example; and source/drain regions 16 and 18 of the second conductivity type, such as n-type, for example.

Buried layer 22 may be formed by an ion implantation process on the material of substrate 12. Alternatively, buried layer 22 can be grown epitaxially on top of substrate 12 or formed through a solid state diffusion process.

The floating body region 24 of the first conductivity type is bounded on top by source line region 16, drain region 18, and insulating layer 62 (or by surface 14 in general), on the sides by insulating layer 26, and on the bottom by buried layer 22. Floating body 24 may be the portion of the original substrate 12 above buried layer 22 if buried layer 22 is implanted. Alternatively, floating body 24 may be epitaxially grown. Depending on how buried layer 22 and floating body 24 are formed, floating body 24 may have the same doping as substrate 12 in some embodiments or a different doping, if desired in other embodiments.

A source line region 16 having a second conductivity type, such as n-type, for example (or p-type, when the first conductivity type is n-type), is provided in floating body region 24, so as to bound a portion of the top of the floating body region in a manner discussed above, and is exposed at surface 14. Source line region 16 may be formed by an implantation process on the material making up substrate 12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion or a selective epitaxial growth process could be used to form source line region 16.

A bit line region 18, also referred to as drain region 18, having a second conductivity type, such as n-type, for example (or p-type, when the first conductivity type is n-type), is also provided in floating body region 24, so as to bound a portion of the top of the floating body region in a manner discussed above, and is exposed at cell surface 14. Bit line region 18 may be formed by an implantation process on the material making up substrate 12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion or a selective epitaxial growth process could be used to form bit line region 18.

A gate 60 is positioned in between the source line region 16 and the drain region 18, above the floating body region 24. The gate 60 is insulated from the floating body region 24 by an insulating layer 62. Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate 60 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.

Insulating layers 26 (like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example, though other insulating materials may be used. Insulating layers 26 insulate memory cell 50 from adjacent memory cell 50. The bottom of insulating layer 26 may reside inside the buried region 22 allowing buried region 22 to be continuous as shown in FIGS. 2 and 3. Alternatively, the bottom of insulating layer 26 may reside below the buried region 22 as in FIGS. 4A and 4B (shown better in FIG. 4A). This requires a shallower insulating layer 28, which insulates the floating body region 24, but allows the buried layer 22 to be continuous in the perpendicular direction of the cross-sectional view shown in FIG. 4A. For simplicity, only memory cell 50 with continuous buried region 22 in all directions will be shown from hereon.

Cell 50 includes several terminals: word line (WL) terminal 70 electrically connected to gate 60, bit line (BL) terminal 74 electrically connected to bit line region 18, source line (SL) terminal 72 electrically connected to source line region 16, buried well (BW) or deep n-well (DNWL) terminal 76 electrically connected to buried layer 22, and substrate terminal 78 electrically connected to the substrate 12. Alternatively, the SL terminal 72 may be electrically connected to region 18 and BL terminal 74 may be electrically connected to region 16.

FIG. 4C further illustrates the conductive or metal lines which form connections to the terminals of the memory cells 50 in the array 100. METAL1 layers 142 form metal lines which are connected to the source/drain regions 16 and 18 through the CONTACT layers 140 (located underneath the METAL1 layers 142 and is not shown in FIG. 4C). Also shown in FIG. 4C are VIA1 layers 144, which later form connections between METAL1 layer and METAL2 layer 146 as shown in FIG. 4D. As illustrated in FIG. 4D, the direction of METAL1 layer 142 and POLY layer 160 define one direction of the memory array (for example the row direction) and METAL2 layer 146 defines another direction of the memory array (for example the column direction).

FIG. 5 illustrates an equivalent circuit representation of memory cell 50. Inherent in memory cell 50 are metal-oxide-semiconductor (MOS) transistor 20, formed by source line region 16, gate 60, bit line region 18, and floating body region 24, and bipolar devices 30a and 30b, formed by buried well region 22, floating body region 24, and source line region 16 or bit line region 18, respectively.

Also inherent in memory device 50 is bipolar device 30c, formed by source line region 16, floating body 24, and bit line region 18. For drawings clarity, bipolar device 30c is shown separately in FIG. 6.

FIG. 7 schematically illustrates an exemplary embodiment of a memory array 100 of memory cells 50 (four exemplary instances of memory cell 50 being labeled as 50a, 50b, 50c and 50d) arranged in rows and columns. In many, but not all, of the figures where array 100 appears, representative memory cell 50a will be representative of a “selected” memory cell 50 when the operation being described has one (or more in some embodiments) selected memory cell(s) 50. In such figures, representative memory cell 50b will be representative of an unselected memory cell 50 sharing the same row as selected representative memory cell 50a, representative memory cell 50c will be representative of an unselected memory cell 50 sharing the same column as selected representative memory cell 50a, and representative memory cell 50d will be representative of an unselected memory cell 50 sharing neither a row or a column with selected representative memory cell 50a.

Several operations can be performed by memory cell 50 such as holding, read, write logic-1 and write logic-0 operations, and have been described in U.S. Patent Application Publication No. 2010/00246284 to Widjaja et al., titled “Semiconductor Memory Having Floating Body Transistor and Method of Operating” (“Widjaja-1”) and U.S. Patent Application Publication No. 2010/0034041, “Method of Operating Semiconductor Memory Device with Floating Body Transistor Using Silicon Controlled Rectifier Principle” (“Widjaja-2”), which are both hereby incorporated herein, in their entireties, by reference thereto.

FIG. 8A schematically illustrates performance of a holding operation on memory array 100, while FIG. 8B shows an example of bias conditions applied on the terminals of a memory cell 50 during a holding operation, according to an exemplary, non-limiting embodiment. A holding operation is performed by applying a positive back bias to the BW terminal 76, zero or negative bias on the WL terminal 70, zero bias on the BL terminal 74, SL terminal 72, and substrate terminal 78. Alternatively, the substrate terminal 78 may be left floating. In another embodiment, one of the SL terminal 72 or BL terminal 74 may be left floating. The positive back bias applied to the buried layer region 22 connected to the BW terminal 76 will maintain the state of the memory cell 50 that it is connected to. The positive bias applied to the BW terminal 76 needs to generate an electric field sufficient to trigger an impact ionization mechanism when the floating body region 24 is positively charged, as will be described through the band diagrams shown in FIGS. 9A and 9B. The impact ionization rate as a function of the electric field is for example described in “Physics of Semiconductor Devices”, Sze S. M. and Ng K. K. (“Sze”), which is hereby incorporated herein, in its entirety, by reference thereto.

In one embodiment the bias conditions for the holding operation on memory cell 50 are: 0 volts is applied to WL terminal 70, 0 volts is applied to BL terminal 74, 0 volts is applied to SL terminal 72, a positive voltage, for example, +1.2 volts is applied to BW terminal 76, and 0 volts is applied to the substrate terminal 78. In other embodiments, different voltages may be applied to the various terminals of memory cell 50 and the exemplary voltages described are not limiting.

FIG. 9A shows an energy band diagram characterizing the intrinsic n-p-n bipolar device 30b when the floating body region 24 is positively charged and a positive bias voltage is applied to the buried well region 22. The vertical dashed lines mark the different regions of the bipolar device 30b. The energy band diagram of the intrinsic n-p-n bipolar device 30a can be constructed in a similar manner, with the source line region 16 (connected to the SL terminal 72) in place of the bit line region 18 (connected to the BL terminal 74). The horizontal dashed lines indicate the Fermi levels in the various regions of the n-p-n transistor 30b. The Fermi level is located in the band gap between the solid line 27 indicating the top of the valence band (the bottom of the band gap) and the solid line 29 indicating the bottom of the conduction band (the top of the band gap) as is well known in the art. If floating body 24 is positively charged, a state corresponding to logic “1”, the bipolar transistors 30a and 30b will be turned on as the positive charge in the floating body region lowers the energy barrier of electron flow (from the source line region 16 or bit line region 18) into the base region (floating body region 24). Once injected into the floating body region 24, the electrons will be swept into the buried well region 22 (connected to BW terminal 76) due to the positive bias applied to the buried well region 22. As a result of the positive bias, the electrons are accelerated and create additional hot carriers (hot hole and hot electron pairs) through an impact ionization mechanism. The resulting hot electrons flow into the BW terminal 76 while the resulting hot holes will subsequently flow into the floating body region 24. When the following condition is met: β×(M−1)≈1—where β is the forward common-emitter current gain of the bipolar transistors 30a or 30b and M is the impact ionization coefficient—the amount of holes injected into the floating body region 24 compensates for the charge lost due to p-n junction forward bias current between the floating body region 24 and the source line region 16 or bit line region 18 and due to holes recombination. This process maintains the charge (i.e. holes) stored in the floating body region 24 which will keep the n-p-n bipolar transistors 30a and 30b on for as long as a positive bias is applied to the buried well region 22 through BW terminal 76.

The region where the product β×(M−1) approaches 1 and is characterized by hole current moving into the base region of a bipolar transistor is sometimes referred to as the reverse base current region and has been described for example in “A New Static Memory Cell Based on Reverse Base Current (RBC) Effect of Bipolar Transistor”, K. Sakui et al., pp. 44-47, International Electron Devices Meeting, 1988 (“Sakui-1”), “A New Static Memory Cell Based on the Reverse Base Current Effect of Bipolar Transistors”, K. Sakui et al., pp. 1215-1217, IEEE Transactions on Electron Devices, vol. 36, no. 6, June 1989 (“Sakui-2”), “On Bistable Behavior and Open-Base Breakdown of Bipolar Transistors in the Avalanche Regime—Modeling and Applications”, M. Reisch, pp. 1398-1409, IEEE Transactions on Electron Devices, vol. 39, no. 6, June 1992 (“Reisch”), all of which are hereby incorporated herein, in their entireties, by reference thereto.

The latching behavior based on the reverse base current region has also been described in a biristor (i.e. bi-stable resistor) for example in “Bistable resistor (Biristor)—Gateless Silicon Nanowire Memory”, J.-W. Han and Y.-K. Choi, pp. 171-172, 2010 Symposium on VLSI Technology, Digest of Technical Papers, 2010 “(“J.-W. Han”), which is hereby incorporated herein, in its entirety, by reference thereto. In a two-terminal biristor device, a refresh operation is still required. J.-W. Han describes a 200 ms data retention for the silicon nanowire biristor memory. In memory cell 50, the state of the memory cell is maintained due to the vertical bipolar transistors 30a and 30b, while the remaining cell operations (i.e. read and write operations) are governed by the lateral bipolar transistor 30c and MOS transistor 20. Hence, the holding operation does not require any interruptions to the memory cell 50 access.

If floating body 24 is neutrally charged (the voltage on floating body 24 being equal to the voltage on grounded bit line region 18), a state corresponding to logic-0, no (or low) current will flow through the n-p-n bipolar devices 30a and 30b. The bipolar devices 30a and 30b will remain off and no impact ionization occurs. Consequently memory cells in the logic-0 state will remain in the logic-0 state.

FIG. 9B shows an energy band diagram of the intrinsic bipolar device 30a when the floating body region 24 is neutrally charged and a bias voltage is applied to the buried well region 22. In this state the energy level of the band gap bounded by solid lines 27A and 29A is different in the various regions of n-p-n bipolar device 30b. Because the potential of the floating body region 24 and the bit line region 18 is equal, the Fermi levels are constant, resulting in an energy barrier between the bit line region 18 and the floating body region 24. Solid line 23 indicates, for reference purposes, the energy barrier between the bit line region 18 and the floating body region 24. The energy barrier prevents electron flow from the bit line region 18 (connected to BL terminal 74) to the floating body region 24. Thus the n-p-n bipolar device 30a and 30b will remain off.

Sakui-1 and Sakui-2 describe a memory cell based on the reverse base current effect, where the base of a n-p-n bipolar transistor is connected to a p-type MOS transistor. Reisch describes the challenges with the memory cell described in Sakui-1 and Sakui-2, which includes the requirement for the current of the p-type MOS transistor. Because the collector terminal of the bipolar transistor also serves as the channel of the p-type MOS transistor, any changes in operating conditions or process conditions will affect both the bipolar transistor and the p-type MOS transistor. For example, increasing the doping level of the collector region will improve the impact ionization efficiency. However, it will also increase the doping level of the p-type MOS transistor channel region, and reduces the drive current of the p-type MOS transistor.

An autonomous refresh for a floating body memory, without requiring to first read the memory cell state, has been described for example in “Autonomous Refresh of Floating Body Cell (FBC)”, Ohsawa et al., pp. 801-804, International Electron Device Meeting, 2008 (“Ohsawa”), U.S. Pat. No. 7,170,807 “Data Storage Device and Refreshing Method for Use with Such Device”, Fazan et al. (“Fazan”), which are hereby incorporated herein, in their entireties, by reference thereto. Ohsawa and Fazan teach an autonomous refresh method by applying periodic gate and drain voltage pulses, which interrupt access to the memory cells being refreshed. In memory cell 50, more than one stable state is achieved because of the vertical bipolar transistors 30a and 30b. The read and write operations of the memory cell 50 are governed by the lateral bipolar transistor 30c and MOS transistor 20. Hence, the holding operation does not require any interruptions to the memory cell 50 access.

In the holding operation described with regard to FIG. 8A, there is no individually selected memory cell. Rather the holding operation will be performed at all cells connected to the same buried well terminal 76. In addition, the holding operation does not interrupt read or write access to the memory cell 50.

FIG. 10 shows a graph of the net current I flowing into or out of the floating body region 24 as a function of the potential V of the floating body 24 (not drawn to scale). A negative current indicates a net current flowing into the floating body region 24, while a positive current indicates a net current flowing out of the floating body region 24. At low floating body 24 potential, between 0V and V_FB0indicated in FIG. 10, the net current is flowing into the floating body region 24 as a result of the p-n diode formed by the floating body region 24 and the buried well region 22 being reverse biased. If the value of the floating body 24 potential is between V_FB0and V_TS, the current will switch direction, resulting in a net current flowing out of the floating body region 24. This is because of the p-n diode, formed by the floating body region 24 and the bit line region 18/source line region 16, being forward biased as the floating body region 24 becomes increasingly more positive. As a result, if the potential of the floating body region 24 is less than V_TS, then at steady state the floating body region 24 will reach V_FB0. If the potential of the floating body region 24 is higher than V_TS, the current will switch direction, resulting in a net current flowing into the floating body region 24. This is as a result of the base current flowing into the floating body region 24 being greater than the p-n diode leakage current formed by the floating body region 24 and the bit line region 18/source line region 16. When the floating body 24 potential is higher than V_FB1, the net current will be out of the floating body region 24. This is because the p-n diode leakage current formed by the floating body region 24 and the bit line region 18/source line region 16 is once again greater than the base current of the bipolar devices 30a and 30b.

The holding operation results in the floating body memory cell having two stable states: the logic-0 state and the logic-1 state separated by an energy barrier, which are represented by V_FB0, V_FB1, and V_TS, respectively. FIG. 11 shows a schematic curve of a potential energy surface (PES) of the memory cell 50, which shows another representation of the two stable states resulting from applying a back bias to the BW terminal 76 (connected to the buried well region 22).

The values of the floating body 24 potential where the current changes direction, i.e. V_FB0, V_FB1, and V_TS, can be modulated by the potential applied to the BW terminal 76. These values are also temperature dependent.

The holding/standby operation also results in a larger memory window by increasing the amount of charge that can be stored in the floating body 24. Without the holding/standby operation, the maximum potential that can be stored in the floating body 24 is limited to the flat band voltage V_FBas the junction leakage current to regions 16 and 18 increases exponentially at floating body potential greater than V_FB. However, by applying a positive voltage to substrate terminal 78, the bipolar action results in a hole current flowing into the floating body 24, compensating for the junction leakage current between floating body 24 and regions 16 and 18. As a result, the maximum charge V_MCstored in floating body 24 can be increased by applying a positive bias to the substrate terminal 78 as shown in FIG. 12. The increase in the maximum charge stored in the floating body 24 results in a larger memory window.

Floating body DRAM cells described in Ranica-1, Ranica-2, Villaret, and Pulicani only exhibit one stable state, which is often assigned as logic-0 state. Villaret describes the intrinsic bipolar transistors enhance the data retention of logic-1 state, by drawing the electrons which otherwise would recombine with the holes stored in the floating body region. However, only one stable state is observed because there is no hole injection into the floating body region to compensate for the charge leakage and recombination.

Memory array 100 may be broken/segmented into multiple sub-arrays. For example, the buried layer region 22 may be segmented to allow for independent memory operation. In one embodiment of the present invention, if the content of a memory sub-array is no longer needed, the holding/standby operation may be terminated by removing the positive bias applied to the BW terminal 76 of that memory sub-array. FIG. 13A is a schematic illustration of the BW segmentation, where memory array 100 is segmented into 4 sub-arrays. Address (ADDR) and control (CNTRL) signals are used to control the operation (and the bias conditions) of the BW terminal 76 of each memory sub-array. A memory sub-array may also be disabled for example if it has been inactive for a certain period of time. A sector enable signal (SCTR_ENBL) may be used to selectively enable or disable a memory sub-array. Inactive sectors will have their associated SCTR_ENBL signals low. Active sectors have their associated SCTR_ENBL signals high.

FIG. 13B illustrates an exemplary BW decoder shown in a sub-array in FIG. 13A. Address (ADDR) and control (CNTRL) signals (for example read operation signal, write operation signal, and standby operation signal) along with a sector enable (SCTR_ENBL) signal provide inputs to the AND gate 210. The output of the AND gate 210 (along with its complementary signal, which is generated by the inverter gate 212) drives the transmission gate 220. The transmission gate 220 selects between VBW_BIAS (for example a positive voltage such as +1.2V) and GND signals as the output to the BW terminal 76 of the memory sub-array (BW_SCTR signal).

As an example, to optimize power management, the SCTR_ENBL signal may be governed by a clock signal. This circuitry would be designed to save power during the low portion of the clock cycle, yet with optimized duty cycle to maintain data integrity during the cycle high time. In another embodiment of the present invention, the BW_SCTR (connected to the BW terminal 76 of the memory sub-array) needs to be set high during certain memory access (for example read and write logic-1 operation). In another example, the BW_SCTR may be set low during other memory operation (for example write logic-0 operation).

The read and write operations of the memory cell have been described, for example, in Widjaja-1 and Widjaja-2. FIGS. 14 and 15 illustrate a read operation performed on an exemplary memory array 100 by applying the following bias conditions: a positive voltage is applied to the selected BW terminal 76a, a positive voltage is applied to the selected BL terminal 74a, zero voltage is applied to the selected SL terminal 72a, a positive voltage applied to the selected WL terminal 70a, while zero voltage is applied to the substrate terminal 78. The positive voltage applied to BL terminal 74 may be less than the positive voltage applied to WL terminal 70, in which the difference in the threshold voltage of the memory cell 50 is employed to represent the state of the memory cell 50. The positive voltage applied to BL terminal 74 may alternatively be greater than or equal to the positive voltage applied to WL terminal 70 and may generate sufficiently high electric field to trigger the bipolar read mechanism. The unselected BL terminals will remain at zero voltage and the unselected WL terminals will remain at zero or negative voltage.

In one particular non-limiting embodiment, about 0.0 volts is applied to selected SL terminal 72a, about +0.4 volts is applied to the selected BL terminal 74a, about +1.2 volts is applied to the selected WL terminal 70a, about +1.2 volts is applied to selected BW terminal 76a, and about 0.0 volts is applied to terminal 78. The unselected terminals 74 remain at 0.0 volts and the unselected terminals 70 remain at 0.0 volts. FIG. 14 shows the bias conditions for the selected memory cell 50a and unselected memory cells 50b, 50c, and 50d in memory array 100. However, these voltage levels may vary.

During a read operation, the selected WL terminal 70a (electrically connected to gate 60) is raised from the initial/standby condition (for example 0.0V) to the read voltage (for example +1.2V). During the rise time of the gate 60 voltage, the surface 14 channel potential will be in non-equilibrium condition as there will be a delay for electrons from source and/or drain regions to drift into the channel region, for example as described in “Substrate Response of a Floating Gate n-Channel MOS Memory Cell Subject to a Positive Linear Ramp Rate”, Han-Sheng Lee and David Scott Lowrie, Solid-State Electronics 24 (3), 1981, pp. 267-273, which is hereby incorporated herein, in its entirety, by reference thereto. The coupling ratio between the gate voltage and the floating body 24 is affected by the rise time of the gate voltage, where a higher ramp rate will result in a higher coupling ratio between the gate 60 voltage and the floating body region 24 potential. During the read operation, the rise time of the gate voltage needs to be controlled so that the increase of the floating body 24 potential by gate 60 to floating body 24 coupling is less than the difference between the transition voltage and the logic-0 voltage (i.e. V_TS−V_FB0) to avoid undesired writing of memory cells 50 in logic-0 state into logic-1 state. The ramp rate during the read operation may be designed to be slower than the ramp rate during the write logic-1 operation, for example by designing the timing of the signals generated by analog supply generation/regulation block 135 (see FIG. 1). The ramp rate may be optimized for different process technology depending on the capacitance between the gate region 60 and the floating body region 24. In one particular non-limiting embodiment, the ramp rate of the gate 60 voltage is designed to be about +1.2V/500 ps. However, this ramp rate may vary, while maintaining a lower ramp rate for the read operation compared to that of the write operation. For example, the ramp rate of the gate 60 voltage may be in the range of about +1.2V/100 ps to +1.2V/2 ns.

During the read operation, the selected BL terminal 74a is also increased from the initial/standby condition (e.g. about 0.0V) to the read voltage (e.g. about +0.4V). During the rise time of the drain region 18, hole current (from the minority carrier of the drain region 18) will flow to the floating body region 24. The hole current is relatively small as it holes are minority carriers. Nevertheless, the rise time of the BL terminal 74a needs to be controlled so that the injected hole can flow out of the floating body region 24 (to the source region 16) to avoid undesired writing of memory cells 50 from logic-0 state to logic-1 state. The ramp rate during the read operation may be designed to be slower than the ramp rate during the write logic-1 operation, for example by designing the timing of the signals generated by analog supply generation/regulation block 135 (see FIG. 1). The ramp rate may be optimized for different process technology depending on the capacitance between the drain region 18 and the floating body region 24. In one particular non-limiting embodiment, the ramp rate of the drain region 18 voltage is designed to be about +0.4V/500 ps. However, this ramp rate may vary, while maintaining a lower ramp rate for the read operation compared to that of the write operation. For example, the ramp rate of the gate 60 voltage may be in the range of about +0.4V/100 ps to +0.4V/2 ns.

The minority hole current (when the drain region 18 is raised to a positive voltage) is inversely proportional to the concentration of a lower-doped region of the p-n junction. The hole current can therefore be reduced by optimizing the concentration of the lower-doped region of the p-n junction. This can be achieved through the optimization of the process steps to form the doping profile of the floating body region 24 and/or the drain region 18, for example through the optimization of the ion implantation dose and energy and/or the subsequent thermal process to activate the dopant. Epitaxial growth process may also be used to form the floating body region 24 and/or the drain region 18.

FIG. 16 schematically illustrates an equivalent capacitor circuit representation of the memory cells shown in FIGS. 2-4. The floating body potential (V_FB) is capacitively coupled with gate oxide capacitance, source side junction capacitance, drain side junction capacitance, and deep n-well junction capacitance. Therefore, the floating body potential (V_FB) can be perturbed by the WL voltage, SL voltage, BL voltage, and BW voltage. As explained in FIG. 10, if the floating body potential V_FBbecomes higher than V_TS, V_FBwill reach V_FB1at steady state. If the V_FBbecomes less than V_TS, V_FBwill reach V_FB0at steady state. When the gate oxide capacitance and the drain side junction capacitance are relatively larger than the deep n-well junction capacitance, V_FBis preferentially controlled by V_WLand V_BL. In this case, V_FBcan become higher than V_TSwithout impact ionization process in the channel as well as V_FBcan become lower than V_TSwithout supplying the forward junction current to the floating body or flowing significantly low forward junction current to the floating body. Therefore, the writing logic-1 and writing logic-0 can be accomplished by capacitive coupling between V_WLand V_BL. The writing mechanism using the capacitive coupling features that the writing logic-1 voltage of V_BLdoes not exceed the impact ionization threshold voltage, which is, in case of silicon semiconductor, 1.2V and the writing logic-0 voltage of V_BLis zero or slightly negative voltage.

FIG. 17 shows a schematic map of word line voltage and bit line voltage that enables V_FBto be higher than V_TSfor writing logic-1 for different V_BW. If V_BWis increased, the depletion width between deep n-well and floating body is increased and BW junction capacitance is decreased. Therefore, the transition voltage V_TSis decreased. Consequently, when V_BWis increased, a relatively lower V_WLand V_BLcan write logic-1 by capacitive coupling, compared to V_WLand V_BLlevels that are required to write logic-1 when V_BWis relatively lower. At a given V_BW, the bias conditions located to the right of the curve represents a write logic-1 bias condition.

FIGS. 18A and 18B illustrate a schematic illustration of a memory array 100, showing a write logic-1 operation which may be performed by applying the following bias conditions: a positive voltage is applied to the selected BW terminal 76a, a positive voltage is applied to the selected BL terminal 74a, zero voltage is applied to the selected SL terminal 72a, a positive voltage is applied to the selected WL terminal 70a, while zero voltage is applied to the substrate terminal 78. The combined capacitive coupling by the positive voltage applied to the selected BL terminal 74a and the positive voltage applied to the selected WL terminal 70a can be sufficiently high enough to raise the V_FBhigher than V_TSso as to trigger an impact ionization mechanism of vertical bipolar transistors 30a and 30b. But the positive voltage applied to the selected BL terminal 74a and the positive voltage applied to the WL selected terminal 70a may not be sufficiently high to trigger an impact ionization mechanism of the lateral bipolar transistor 30c and MOS transistor 20. The combined capacitive coupling by the positive voltage applied to the selected BL terminal 74a and the zero voltage applied to the unselected WL terminals 70n can be insufficient to write logic-1. The combined capacitive coupling by the zero voltage applied to the unselected BL terminal 74n and the positive voltage applied to the selected WL terminals 70a can be insufficient to write logic-1.

FIGS. 19A and 19B show a write logic-1 operation according to another embodiment of the present invention, where the following bias conditions are applied to the memory array 100: a positive voltage is applied to the selected BW terminal 76a, a positive voltage is applied to the selected BL terminal 74a, a positive voltage is applied to the selected SL terminal 72a, a positive voltage is applied to the selected WL terminal 70a, while zero voltage is applied to the substrate terminal 78. The combined capacitive coupling by the positive voltage applied to the selected BL terminal 74a, selected SL terminal 72, and the selected WL terminal 70a can be sufficiently high to raise the V_FBhigher than V_TSso as to trigger impact ionization mechanism of vertical bipolar transistors 30a and 30b.

In one particular non-limiting embodiment, the selected WL terminal 70a (electrically connected to gate 60) is increased from the initial/standby condition (e.g. about 0.0V) to the write condition (e.g. about +0.8V), while the selected BL terminal 74a (electrically connected to drain 18) and selected SL terminal 72a (electrically connected to source 16) is increased from the initial/standby condition (e.g. about 0.0V) to the write condition (e.g. about +0.3V). As described, the coupling ratio between the gate electrode 60 and the floating body region 24 is a function of the ramp rate. As a result, a higher ramp rate may assist the write logic-1 operation. However, the voltage ramp rate of the WL terminal 70a also has to be controlled to avoid undesired writing of unselected memory cells 50 in the selected row from logic-0 state to logic-1 state. Similarly, the voltage ramp rate of the BL terminal 74a and SL terminal 72a may also assist the write logic-1 operation. However, the voltage ramp rate of the BL terminal 74a and SL terminal 72a also have to be controlled to avoid undesired writing of unselected memory cells 50 in the selected column from logic-0 state to logic-1 state, for example by designing the timing of the signals generated by analog supply generation/regulation block 135 (see FIG. 1). The ramp rate may be optimized for different process technology depending on the capacitance between the drain region 18 and the floating body region 24. In one particular non-limiting embodiment, the ramp rate of the drain region 18 voltage is designed to be about +0.8V/200 ps. However, this ramp rate may vary, while maintaining a lower ramp rate for the read operation compared to that of the write operation. For example, the ramp rate of the gate 60 voltage may be in the range of about +0.8V/20 ps to +0.8V/2 ns.

FIG. 20 shows a schematic map of word line voltage and bit line voltage that enables a floating body potential to be lower than a transition voltage for write logic-0. At given V_BW, the writing logic-0 can be accomplished by application of the voltage from left and down side of the curve. If V_BWis increased, the positive floating body charge density becomes higher due to the impact ionization of vertical bipolar transistors 30a and 30b. Therefore the higher forward-biased junction current and thus a more negative V_BLis necessary to write logic-0. When V_BLis highly negative such as −1V, then the forward-biased junction current is predominant so that the all cells connected to the BL shall be written logic-0 regardless of WL voltage. However, if V_BLis negative and reasonably small such as −0.2V, the gate capacitive coupling can influence the write logic-0 process. At a fixed V_BW, when V_WLis decreased, V_FBbecomes lowered due to the capacitive coupling. In this case, the less forward-biased junction current can pull down V_FBbelow V_TS, which implies that a lower V_WLcan be used to write logic-0. Conversely, when V_WLis increased, V_FBbecomes increased and the same forward-biased junction current may not sufficient to pull down V_FBbelow V_TS. Therefore, the bit-selective write logic-0 can be accomplished at fixed negative V_BLby choosing a V_WLlower than the curve for a selected row and a V_WLhigher than the curve for the unselected row(s).

FIGS. 21 and 22 are schematic illustrations of a memory array 100 and selected memory cell 50, respectively, showing a write logic-0 operation which may be performed through an application of a zero or negative voltage to the selected WL terminal 70a, a negative voltage to selected BL terminal 74a, zero or a positive voltage to the selected BW terminal 76a, zero voltage to the selected SL terminal 72a, and zero or positive voltage to substrate terminal 78. Under these conditions, the floating body 24 potential will decrease through capacitive coupling from the zero or negative voltage applied to the WL terminal 70a. The decrease of floating body 24 potential facilitates the forward junction current by the negative voltage applied to the BL terminal 74, which facilitates pulling the floating body potential below bit transition voltage and thus the cessation of the impact ionization mechanism of vertical bipolar transistors 30a and 30b. Despite the negative voltage applied to the selected BL terminal 74a, the positive voltage applied to the unselected WL terminals 70n can increase floating body potential and thus the forward junction current by the negative voltage applied to the BL terminal 74 may be insufficient to write logic-0. The capacitive coupling from zero voltage applied to the unselected BL terminal 74n and the zero or negative voltage applied to the selected WL terminals 70a can be insufficient to write logic-0.

The selected WL terminal 70a (electrically connected to gate 60) is decreased from the initial/standby condition (e.g. about 0.0V) to the write condition (e.g. about −0.1V). The selected BL terminal 74a (electrically connected to drain 18) is increased from the initial/standby condition (e.g. about 0.0V) to the write condition (e.g. about −0.2V). The unselected WL terminals 70n (electrically connected to gate) are increased from initial/standby condition (e.g. about 0.0V) to the write inhibit condition (e.g. about +0.3V). Similar to that of the read operation, the coupling ratio between the gate electrode 60 and the floating body region 24 is a function of the ramp rate. The voltage ramp rate of the unselected WL terminal 70n also has to be controlled to avoid undesired writing of unselected memory cells 50 in the unselected row from logic-0 state to logic-1 state. The ramp rate may be optimized for different process technology depending on the capacitance between the gate region 60 and the floating body region 24. In one particular non-limiting embodiment, the ramp rate of the gate 60 voltage is designed to be about +0.3V/200 ps. However, this ramp rate may vary, while maintaining a lower ramp compared to that of the write logic-1 operation. For example, the ramp rate of the gate 60 voltage may be in the range of about +0.3V/20 ps to +0.3V/2 ns.

FIGS. 23 and 24 illustrate a schematic illustration of a memory array 100, showing a write logic-0 operation according to another embodiment of the present invention, which may be performed through an application of a positive voltage to the selected WL terminal 70a, a negative voltage to selected BL terminal 74a, zero or a positive voltage to the selected BW terminal 76a, zero voltage to the selected SL terminal 72a, and zero or positive voltage to substrate terminal 78. Under these conditions, the floating body 24 potential will increase through capacitive coupling from the positive voltage applied to the WL terminal 70. As a result of the floating body 24 potential increase and the negative voltage applied to the BL terminal 74, the p-n junction between 24 and 18 is forward-biased, evacuating any holes from the floating body 24.

The selected WL terminal 70a (electrically connected to gate 60) is raised from the initial/standby condition (for example 0.0V) to the write logic-0 voltage (for example +1.2V). As has been described above, the coupling ratio between the gate electrode 60 and the floating body region 24 is a function of the ramp rate. As a result, a higher ramp rate may assist the write logic-0 operation. However, the voltage ramp rate of the WL terminal 70a also has to be controlled to avoid undesired writing of unselected memory cells 50 in the selected row from logic-0 state to logic-1 state. The ramp rate may be optimized for different process technology depending on the capacitance between the gate region 60 and the floating body region 24. In one particular non-limiting embodiment, the ramp rate of the gate 60 voltage is designed to be about +1.2V/200 ps. However, this ramp rate may vary, while maintaining a lower ramp compared to that of the write logic-1 operation. For example, the ramp rate of the gate 60 voltage may be in the range of about +1.2V/20 ps to +1.2V/2 ns.

After the write logic-0 operation is finished, the potential of the BL terminal 74 is raised from the negative voltage (e.g. about −0.2V) to its standby condition (e.g. about 0.0V). The ramp rate of the BL terminal 74 needs to be controlled to avoid undesired writing of unselected memory cells 50 in the selected column from logic-0 state to logic-1 state as well as undesired reverting of written bit state of the selected memory cell.

FIGS. 25 and 26 illustrate a write logic-0 operation according to another embodiment of the present invention. A slight positive voltage is applied to the selected BL terminal 74a and SL terminal 72a. This achieves a similar effect as reducing the V_BWas this reduces the potential difference between the BW terminal 76 and the SL and BL terminals 72a and 74a, respectively. A write logic-0 can then be performed to the selected memory cell 50 by lowering the voltage of selected WL terminal 70a, which will lower V_FBthrough capacitive coupling.

In one embodiment, the following bias conditions are applied: the selected WL terminal 70a is decreased from the initial/standby condition (e.g. about 0.0V) to the write condition (e.g. about −0.2V). The selected SL terminal 72a and BL terminal 74a are increased to the write condition (e.g. about +0.2V) from the initial/standby condition (e.g. about 0.0V).

FIG. 27 shows a schematic map of word line voltage and bit line voltage for holding logic-1 states. At given V_BW, if the bias voltage is formed from left and down side of the curve, the logic-1 states turned to logic-0 state by writing logic-0 mechanism. In practice, the BL voltage for holding is zero in order to not flow BL current. Likewise, the WL voltage for holding tends to be zero in order to shut-off the unselected bit cells. However, if the V_DNWLis sufficiently decreased while keeping the data retention capability, the zero voltage to WL may lose logic-1 state even without involving the forward-biased junction current because the capacitive coupling from the gate 60 is solely sufficient to pull down V_FBbelow V_TS. However, the DNWL current to hold logic-1 at low positive V_DNWLand positive V_WLcan be less than that at high V_DNWLand zero V_WL. With this regards, low V_DNWLholding and positive V_WLfor holding condition can be applied for low-power stand-by mode.

FIG. 28 schematically illustrates a holding operation performed on a memory array according to another embodiment of the present invention. In one embodiment the bias conditions for the holding operation on memory cell 50 are: +0.2 volts is applied to WL terminal 70, 0 volts is applied to BL terminal 74, 0 volts is applied to SL terminal 72, a positive voltage, for example, +1.0 volts is applied to BW terminal 76, and 0 volts is applied to the substrate terminal 78. In other embodiments, different voltages may be applied to the various terminals of memory cell 50 and the exemplary voltages described are not limiting.

The source and drain capacitance may be increased to improve the coupling of the source and drain potential to the floating body potential. FIGS. 29A and 29B illustrate exemplary layout views of memory cells 50 with increased source and drain capacitive coupling to the floating body region 24. The length of the source and drain regions 16 and 18 (L16 and L18) may be drawn longer than the length of the floating body region 24 (L24) (underneath the gate region 60). In one embodiment, the ratio of the L16 (and L18) and L24 may be greater than two. The ratio may be optimized for different process technology depending on the capacitance between the source/drain region 16/18 and the floating body region 24.

FIG. 29B illustrates another layout view of memory cells 50, where the source/drain regions are drawn wider than the floating body region 24.

FIG. 30 illustrates another layout view of another memory array 100 according to another embodiment of the present invention. The memory array 100 includes an additional dummy POLY layer 160D which does not overlay a DIFF region 130 (hence being referred to as dummy layer). The dummy layer 160D for example may be a result of restrictive design rules (which guides the layout drawing of the layers) for better lithography patterning process. As shown in FIG. 30, the unit cell of the memory cell 50 comprises two POLY 160 regions, one 160D to define the dummy region and another 160 to define the transistor region (overlapping with DIFF layer 130).

FIGS. 31 to 34 illustrate a lithography process using cut mask to form the layers constructing the memory cell 50 and memory array 100. FIG. 31 illustrates formation of DIFF layers 130A having regular line width and spacing. The DIFF layers 130A may be formed using any lithography techniques including single exposures, multiple patterning techniques such as multiple litho and multiple etch techniques or self-aligned double patterning processes or directed self-assembly for example such as described in Finders, Jo, et al. “Double patterning for 32 nm and below: an update”, SPIE Advanced Lithography, International Society for Optics and Photonics, 2008 and Park, Sang-Min, et al. “Sub-10 nm nanofabrication via nanoimprint directed self-assembly of block copolymers”, ACS nano 5.11 (2011): 8523-8531, which are hereby incorporated herein, in their entireties, by reference thereto. A cut mask layer 130B (see FIG. 32), which may also have regular line width and spacing, is then used to cut the patterns formed using the DIFF layers 130A resulting in the final structures shown in FIG. 33. POLY layers 160 can then be used to define the gate regions in subsequent process as shown in FIG. 34. The line formation followed by line cut may also be employed to form the POLY layers 160 (as well as other layers used in the fabrication of the memory array 100 and the integrated circuit 1000).

FIGS. 35 and 36 illustrate a schematic layout view of memory array 100 according to another embodiment of the present invention where the DIFF layers 130 are arranged in a staggered or zig-zag pattern. As a result, memory cells in adjacent columns do not share the same POLY layer 160. In the example illustrated in FIG. 36, the first POLY layer 160 is connected to WL terminal 70a and the second POLY layer 160 is connected to WL terminal 70b, while the first METAL2 layer 146 is connected to BL terminal 74a and the second METAL2 layer 146 is connected to BL terminal 74b. As can be seen, memory cells in adjacent columns (for example memory cells 50a and 50b) are connected to different WL terminals (memory cells 50a and 50b are connected to WL terminals 70b and 70a, respectively). This is also illustrated in the equivalent circuit representation of the memory array 100 in FIG. 37. The memory array 100 shown in FIG. 37 may also be referred to as folded memory array architecture.

The folded memory array architecture allows the use of adjacent BL as a reference. In an exemplary read operation illustrated in FIG. 38, the state of memory cell 50a is being sensed. To perform the read operation, the following bias conditions are applied to the selected memory cell 50a: a positive voltage is applied to the BW terminal 76a, zero voltage is applied to the selected SL terminal 72a, a positive voltage (or more positive than the voltage applied to unselected WL terminals) applied to the selected WL terminal 70a, while zero voltage is applied to the substrate terminal 78a. The following bias conditions are applied to the unselected memory cells: a positive voltage is applied to the BW terminal 76, zero voltage is applied to the unselected SL terminal 72, zero voltage is applied to the unselected BL terminal 74, zero voltage (or more negative than the voltage applied to the selected WL terminal 70a) is applied to the unselected WL terminal 70, while zero voltage is applied to the substrate terminal.

The selected BL terminal and the BL terminal directly adjacent to it, for example BL terminals 74a and 74b are pre-charged to a positive voltage, for example Vdd/2. After the pre-charge operation, the charge on the selected BL terminal 74a may or may not be discharged depending on the state of the memory cell 50a. If memory cell 50a is in logic-1 state having a higher conductance, then the charge on the BL terminal 74a will be discharged through the memory cell 50a. If memory cell 50a is in logic-0 state having a lower conductance, then the charge on the BL terminal 74a will be discharged slower compared to if the memory cell 50a is in logic-1 state. Because all the memory cells connected to the BL terminal 74b are unselected (all the unselected WL terminals 70 are turned off), the BL terminal 74b will not be discharged through the unselected memory cells. A sensing circuit, for example a sense amplifier, can then be used to compare the charge of the BL terminals 74a and 74b.

In one particular non-limiting embodiment, about 0.0 volts is applied to the selected SL terminal 72ab, about +1.2 volts is applied to the selected WL terminal 70a, about +1.2 volts is applied to BW terminal 76, and about 0.0 volts is applied to terminal 78, as illustrated in FIG. 38. The unselected SL terminals 72 remain at 0.0 volts, the unselected BL terminals 74 (other than the adjacent BL terminal 74b) are biased at 0.0 volts, and the unselected WL terminals 70 remain at 0.0 volts as illustrated in FIG. 38. The selected BL terminal 74a and the adjacent BL terminal 74b are then precharged to +0.4 volts. However, these voltage levels may vary while maintaining the relative relationships between voltage levels as generally described above.

FIG. 39 schematically illustrates a self-reference read scheme that may be used to read the state of the memory cell 50 according to an embodiment of the present invention. In this read scheme, a set of bias conditions {V₁} is applied to the selected memory cell 50a. A property of the selected memory cell 50a, for example the drain current I_BL1(flowing from the BL terminal 74a to the SL terminal 72a) is obtained. A second set of bias conditions is then applied to the selected memory cell 50a {V₂} and the same property of the selected memory cell 50a is then measured again, for example the drain I_BL2. The change in the drain current (I_BL2−I_BL1) due to the change in the applied bias conditions {V₂−V₁} depends on the state of the selected memory cell 50a, where (I_BL2−I_BL1) is greater when the selected memory cell 50a is in logic-1 state compared to when the selected memory cell 50a is in logic-0 state. Therefore, the change in the property of the selected memory cell 50a as a result of the change in the applied bias conditions may be used to sense the state of the memory cell 50.

In one particular non-limiting embodiment, the first bias conditions {V₁} are as follows: about 0.0 volts is applied to selected SL terminal 72a, about +0.4 volts is applied to the selected BL terminal 74a, about +1.2 volts is applied to the selected WL terminal 70a, about +1.2 volts is applied to selected BW terminal 76a, and about 0.0 volts is applied to terminal 78. The unselected terminals 74 remain at 0.0 volts, the unselected terminals 72, and the unselected terminals 70 remain at 0.0 volts. A property of the selected memory cell 50a, for example the drain current I_BL1(flowing from the BL terminal 74a to the SL terminal 72a) is obtained. A second set of bias conditions {V₂} is then applied to the selected memory cell 50a, for example by increasing the V_BWapplied to the selected BW terminal 76a. In one particular non-limiting embodiment, the voltage applied to the selected BW terminal 76a is increased to about +1.3 volts, while the same bias conditions are applied to the other terminals: about 0.0 volts is applied to selected SL terminal 72a, about +0.4 volts is applied to the selected BL terminal 74a, about +1.2 volts is applied to the selected WL terminal 70a, and about 0.0 volts is applied to terminal 78. The same property of the selected memory cell 50a (for example the drain current) is then measured again I_BL2. The change in the drain cell current (I_BL2−I_BL1) is greater if the selected memory cell 50a is in logic-1 state compared to when the selected memory cell 50a is in logic-0 state. The change in drain cell current may be optimized for different process technology. In one particular non-limiting embodiment, almost no (or very small) cell current change (for example, less than 100 nA) is observed if selected memory cell 50a is in logic-0 state, and 5 μA cell current change is observed if selected memory cell 50a is in logic-1 state. However, the resulting cell current change may vary, which may be a result of different bias conditions and/or the process steps forming the memory cell 50, for example the ion implantation dose and energy forming the floating body region 24 and/or the buried region 22 and the thermal annealing step. For example, less than 500 nA cell current change may be observed for memory cell in logic-0 state and between 100 nA and 50 μA difference may be observed for memory cell in logic-1 state.

In another embodiment, the V_BWis kept the same in the second bias conditions, and the bias conditions to the other terminals are changed. For example, second bias conditions may be applied as follows: about −0.1 volts is applied to the selected SL terminal 72a, about +0.3 volts is applied to the selected BL terminal 74a, about +1.1 volts is applied to the selected WL terminal 70a, about +1.2 volts is applied to the selected BW terminal 76a, and about 0.0 volts is applied to the substrate terminal 78. The drain current I_BL(flowing from the BL terminal 74a to the SL terminal 72a) is then compared. The difference in the drain cell current (I_BL2−I_BL1) is greater if the selected memory cell 50a is in logic-1 state compared to when the selected memory cell 50a is in logic-0 state.

FIG. 40 schematically illustrates a self-reference read scheme that may be used to read the state of the memory cell 50 according to another embodiment of the present invention. In this scheme, four sets of bias conditions ({V₁}, {V₂}, {V₃}, and {V₄}) are applied to the selected memory cell 50a. In this read scheme, two sets of the bias conditions, for example {V₁} and {V₃}, are used to measure the background noise information. In one embodiment, in order to measure the background noise, the same bias conditions are applied to the selected and unselected cells. The other two sets of bias conditions, for example {V₂} and {V₄}, are used to measure the change in the selected cell properties (for example the drain current I_BL) due to the change in the bias conditions.

In one particular non-limiting embodiment, a first set of bias conditions {V₁} is as follows: about 0.0 volts is applied to selected SL terminal 72a, about +0.4 volts is applied to the selected BL terminal 74a, about 0.0 volts is applied to the selected WL terminal 70a, about +1.2 volts is applied to selected BW terminal 76a, and about 0.0 volts is applied to terminal 78. The unselected terminals 74 remain at 0.0 volts, the unselected terminals 72, and the unselected terminals 70 remain at 0.0 volts. I_BL1can then be measured and is a measure of the current contribution from the unselected cells along the selected BL 74a.

A second set of bias conditions {V₂} is as follows: about 0.0 volts is applied to selected SL terminal 72a, about +0.4 volts is applied to the selected BL terminal 74a, about +1.2 volts is applied to the selected WL terminal 70a, about +1.2 volts is applied to selected BW terminal 76a, and about 0.0 volts is applied to terminal 78. The unselected terminals 74 remain at 0.0 volts, the unselected terminals 72, and the unselected terminals 70 remain at 0.0 volts. The drain current I_BL2can then be measured.

The bias conditions applied to the memory array 100 can then be modified. For example, the V_BWapplied to the selected BW terminal 76 may be increased in {V₃} and {V₄}. Non-limiting bias conditions {V₃} are as follows: about 0.0 volts is applied to selected SL terminal 72a, about +0.4 volts is applied to the selected BL terminal 74a, about 0.0 volts is applied to the selected WL terminal 70a, about +1.3 volts is applied to selected BW terminal 76a, and about 0.0 volts is applied to terminal 78. The unselected terminals 74 remain at 0.0 volts, the unselected terminals 72, the unselected terminals 76 remain at +1.2 volts, and the unselected terminals 70 remain at 0.0 volts. I_BL3can then be measured and is a measure of the current contribution from the unselected cells along the selected BL 74a when V_BWis changed.

A non-limiting set of bias conditions {V₄} is as follows: about 0.0 volts is applied to selected SL terminal 72a, about +0.4 volts is applied to the selected BL terminal 74a, about +1.2 volts is applied to the selected WL terminal 70a, about +1.3 volts is applied to selected BW terminal 76a, and about 0.0 volts is applied to terminal 78. The unselected terminals 74 remain at 0.0 volts, the unselected terminals 72, the unselected terminals 76 remain at +1.2 volts, and the unselected terminals 70 remain at 0.0 volts. The drain current I_BL4can then be measured.

The measured properties ((I_BL4−I_BL2)−(I_BL3−I_BL1)) reflect the state of the selected memory cell 50a while removing the background noise information due to the unselected cells along the selected BL terminal 74a. The difference in drain currents ((I_BL4−I_BL2)−(I_BL3−I_BL1)) is higher when the selected memory cell 50a is in the logic-1 state compared to when the selected memory cell 50a is in the logic-0 state. The change in drain cell current may be optimized for different process technology. In one particular non-limiting embodiment, almost no (or very small) cell current change (for example, less than 100 nA) is observed if selected memory cell 50a is in logic-0 state, and 5 μA cell current change is observed if selected memory cell 50a is in logic-1 state. However, the resulting cell current change may vary, which may be a result of different bias conditions and/or the process steps forming the memory cell 50, for example the ion implantation dose and energy forming the floating body region 24 and/or the buried region 22 and the thermal annealing step. For example, less than 500 nA cell current change may be observed for memory cell in logic-0 state and between 100 nA and 50 μA difference may be observed for memory cell in logic-1 state.

FIGS. 41 and 42 illustrate a vertical channel memory cell 250 according to another embodiment of the present invention. Memory cell 250 includes a substrate 12 of a first conductivity type such as p-type, for example (alternatively, first conductivity type could be n-type). Substrate 12 is typically made of silicon, but may also comprise, for example, germanium, silicon germanium, gallium arsenide, carbon nanotubes, and/or other semiconductor materials. In some embodiments of the invention, substrate 12 can be the bulk material of the semiconductor wafer. In another embodiment, as shown in FIG. 42, substrate 12A of a first conductivity type (for example, p-type) can be a well of the first conductivity type embedded in a well 29 of the second conductivity type, such as n-type (alternatively, second conductivity type is p-type when first conductivity type is n-type). The well 29 in turn can be another well inside substrate 12B of the first conductivity type (for example, p-type). In another embodiment, well 12A can be embedded inside the bulk of the semiconductor wafer of the second conductivity type (for example, n-type). These arrangements allow for segmentation of the substrate terminal, which is connected to region 12A. To simplify the description, the substrate 12 will usually be drawn as the semiconductor bulk material as it is in FIG. 41.

Memory cell 250 also includes a bit line region 18 of a second conductivity type, such as n-type, for example; a floating body region 24 of the first conductivity type, such as p-type, for example; a source line region 16 of the second conductivity type, such as n-type, for example; and an charge injector region 22 of the second conductivity type, such as n-type, for example.

Bit line region 18 may be formed by an ion implantation process on the material of substrate 12. Alternatively, bit line region 18 can be grown epitaxially on top of substrate 12 or formed through a solid state diffusion process.

The floating body region 24 of the first conductivity type is bounded on top by source line region 16 and charge injector region 32, on the sides by insulating layer 26 (located on a plane to the front of and behind the floating body region 24—not shown in FIGS. 41-42), on the sides by dielectric layer 62 and gate 60, and on the bottom by bit line region 18. Floating body 24 may be the portion of the original substrate 12 above bit line region 18 if bit line region 18 is implanted. Alternatively, floating body 24 may be epitaxially grown. Depending on how bit line region 18 and floating body 24 are formed, floating body 24 may have the same doping as substrate 12 in some embodiments or a different doping, if desired in other embodiments.

A source line region 16 having a second conductivity type, such as n-type, for example, is provided in floating body region 24, so as to bound a portion of the top of the floating body region in a manner discussed above, and is exposed at surface 14. Source line region 16 may be formed by an implantation process on the material making up substrate 12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion or a selective epitaxial growth process could be used to form source line region 16.

A charge injector 32 having a second conductivity type, such as n-type, for example, is also provided in floating body region 24, so as to bound a portion of the top of the floating body region in a manner discussed above, and is exposed at cell surface 14. Charge injector region 32 may be formed by an implantation process on the material making up substrate 12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion or a selective epitaxial growth process could be used to form injector region 22

A gate 60 is positioned in between the source line region 16 and the drain region 18, on the sides of the floating body region 24. The gate 60 is insulated from the floating body region 24 by an insulating layer 62. Insulating layer 62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate 60 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.

Insulating layers 26 (like, for example, shallow trench isolation (STI)), may be made of silicon oxide, for example, though other insulating materials may be used. Insulating layers 26 insulate memory cell 250 from adjacent memory cell 250. The bottom of insulating layer 26 may reside below the bit line region 18 to allow for the bit line region 18 to be continuous in one direction and discontinuous in the other direction. This requires a deeper insulating layer 28 (not shown), which insulates the floating body region 24, but allows the bit line region 18 to be discontinuous in the perpendicular direction of the cross-sectional view shown in FIGS. 41 and 42.

Cell 250 includes several terminals: word line (WL) terminal 70 electrically connected to gate 60, bit line (BL) terminal 74 electrically connected to drain region 18, source line (SL) terminal 72 electrically connected to source line region 16, charge injector (CI) terminal 86 electrically connected to charge injector region 32, and substrate (SUB) terminal 78 electrically connected to the substrate 12.

FIG. 43 illustrates an equivalent circuit representation of memory cell 250. Inherent in cell 250 is metal-oxide-semiconductor (MOS) transistor 20a formed by source line region 16, gate 60, drain region 18, and floating body region 24. In addition, bipolar transistor 30a formed by source line region 16, floating body region 24, and injector region 32 is also inherent in cell 250. Similarly, MOS transistors 20b—formed by charge injector region 32, gate 60, drain region 18, and floating body region 24—is also inherent in cell 250, as shown in FIG. 43.

In the operation of memory cell 250, the bipolar transistor 30a and/or the transistor 20b is used to maintain the state stored in memory cell 250, while the other transistor 20a is used for the other operations, such as read and write operations.

FIG. 44 illustrates a holding operation being performed on a selected memory cell 250. The holding operation is performed by applying a positive bias to the CI terminal 76, zero or low negative bias on the WL terminal 70 to turn-off the channel region between the bit line region 18 of the memory cell 250 and the injector region 22, and zero bias on the SL terminal 72, SUB terminal 78, and BL terminal 74. The positive bias applied to the charge injector region 22 connected to the CI terminal 76 will maintain the state of the memory cell 250 that it is connected to by maintaining the charge stored in the floating body region 24. The positive bias applied to the CI terminal 76 needs to generate an electric field sufficient to trigger an impact ionization mechanism when the floating body region 24 is positively charged, as will be described through the band diagram shown in FIGS. 45A and 45B.

FIG. 45A shows an energy band diagram characterizing the intrinsic n-p-n bipolar device 30a formed by source line region 16, floating body region 24, and injector region 32, when the floating body region 24 is positively charged and a positive bias voltage is applied to the charge injector region 32. The vertical dashed lines mark the different regions of the bipolar device 30a. The horizontal dashed lines indicate the Fermi levels in the various regions of the n-p-n transistor 30a. The Fermi level is located in the band gap between the solid line 27 indicating the top of the valence band (the bottom of the band gap) and the solid line 29 indicating the bottom of the conduction band (the top of the band gap) as is well known in the art. If floating body 24 is positively charged, a state corresponding to logic “1”, the bipolar transistor 30a will be turned on as the positive charge in the floating body region 24 lowers the energy barrier of electron flow from the source line region 16 into the base region (floating body region 24). Once injected into the floating body region 24, the electrons will be swept into the charge injector region 32 (connected to CI terminal 86) due to the positive bias applied to the charge injector region 32. As a result of the positive bias, the electrons are accelerated and create additional hot carriers (hot hole and hot electron pairs) through an impact ionization mechanism. The resulting hot electrons flow into the CI terminal 86 while the resulting hot holes will subsequently flow into the floating body region 24. When the following condition is met: β×(M−1)≈1—where β is the forward common-emitter current gain of the bipolar transistor 30a and M is the impact ionization coefficient—the amount of holes injected into the floating body region 24 compensates for the charge lost due to p-n junction forward bias current between the floating body region 24 and the source line region 16 or bit line region 18 and due to holes recombination. This process maintains the charge (i.e. holes) stored in the floating body region 24 which will keep the n-p-n bipolar transistor 30a on for as long as a positive bias is applied to the charge injector region 32 through CI terminal 86.

If floating body 24 is neutrally charged (the voltage on floating body 24 being equal to the voltage on grounded source line region 16), a state corresponding to logic-0, no (or low) current will flow through the n-p-n bipolar device 30a. The bipolar device 30a will remain off and no impact ionization occurs. Consequently memory cells in the logic-0 state will remain in the logic-0 state.

FIG. 45B shows an energy band diagram of the intrinsic bipolar device 30a when the floating body region 24 is neutrally charged and a bias voltage is applied to the charge injector region 32. In this state the energy level of the band gap bounded by solid lines 27A and 29A is different in the various regions of n-p-n bipolar device 30a. Because the potential of the floating body region 24 and the source line region 16 is equal, the Fermi levels are constant, resulting in an energy barrier between the source line region 16 and the floating body region 24. Solid line 23 indicates, for reference purposes, the energy barrier between the source line region 16 and the floating body region 24. The energy barrier prevents electron flow from the source line region 16 (connected to SL terminal 72) to the floating body region 24. Thus the n-p-n bipolar device 30a will remain off.

FIG. 46 illustrates an exemplary set of bias conditions for performing a read operation on the memory cell 250 according to an embodiment of the present invention. The read operation is performed by applying the following bias conditions: a positive bias to the WL terminal 70, a positive bias to the BL terminal 74, zero bias to the SL terminal 72, zero or positive bias to the CI terminal 86, and zero bias to the substrate terminal 78. All unselected WL terminals 70 (not shown) have zero or negative bias applied, all unselected BL terminals 74 (not shown) have zero volts applied, all unselected SL terminals 72 (not shown) have zero volts applied, and all unselected CI terminals 86 have zero or positive bias applied.

In one embodiment, the bias conditions for the read operation for memory cell 250 are: about +1.2 volts is applied to WL terminal 70, about +0.4 volts is applied to BL terminal 74, about 0.0 volts is applied to SL terminal 72, about +1.2 volts is applied to CI terminal 86, and about 0.0 volts is applied to substrate terminal 78. In other embodiments, different voltages may be applied to the various terminals of memory cell 250 and the exemplary voltages described are not limiting. The positive voltage applied to BL terminal 74 may be less than the positive voltage applied to WL terminal 70, in which the difference in the threshold voltage of the memory cell 250 is employed to represent the state of the memory cell 250. The positive voltage applied to BL terminal 74 may also be greater than or equal to the positive voltage applied to WL terminal 70 and may generate sufficiently high electric field to trigger the bipolar read mechanism.

A sensing circuit typically connected to BL terminal 74 can be used to determine the data state of the memory cell 250. Any sensing scheme known in the art can be used in conjunction with memory cell 250.

FIG. 47 is a schematic illustration of a memory cell 250 showing exemplary bias conditions for a write logic-1 operation on the memory cell 250 through an impact ionization mechanism, according to an embodiment of the present invention. The following bias conditions are applied: a positive voltage is applied to the selected WL terminal 70, a positive voltage is applied to the selected BL terminal 74, zero voltage is applied to the selected SL terminal 72, zero or positive voltage is applied to the selected CI terminal 86, and zero voltage is applied to the substrate terminal 78. This positive voltage applied to the selected BL terminal 74 is greater than or equal to the positive voltage applied to the selected WL terminal 70 and may generate a sufficiently high electric field to trigger an impact ionization mechanism.

In one particular non-limiting embodiment, about +1.2 volts is applied to the selected WL terminal 70, about +1.2 volts is applied to the selected BL terminal 74, about 0.0 volts is applied to SL terminal 72, about 0.0 volts or +1.2 volts is applied to CI terminal 86, and about 0.0 volts is applied to substrate terminal 78; while about 0.0 volts is applied to the unselected WL terminals 70, unselected BL terminals 74, unselected SL terminals, and substrate terminal 78, and 0.0 volts or +1.2 volts is applied to unselected CI terminal 86. These voltage levels are exemplary only and may vary from embodiment to embodiment. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting.

FIG. 48 is a schematic illustration showing bias conditions for a write logic-1 operation using band-to-band tunneling mechanism performed on memory cell 250 according to an embodiment of the present invention. A write logic-1 operation using band-to-band tunneling mechanism can be performed by applying the following bias conditions: a negative voltage is applied to the selected WL terminal 70, a positive voltage is applied to the selected BL terminal 74, zero voltage is applied to the selected SL terminal 72, zero or positive voltage is applied to the selected CI terminal 86, and zero voltage is applied to the substrate terminal 78.

In one particular non-limiting embodiment, about −1.2 volts is applied to the selected WL terminal 70, about +1.2 volts is applied to the selected BL terminal 74, about 0.0 volts is applied to selected SL terminal 72, about 0.0 volts or +1.2 volts is applied to selected CI terminal 86, and about 0.0 volts is applied to substrate terminal 78; while about 0.0 volts is applied to the unselected WL terminals 70, unselected BL terminals 74, unselected SL terminals 72, and substrate terminal 78, and 0.0 volts or +1.2 volts is applied to unselected CI terminals 86. These voltage levels are exemplary only may vary from embodiment to embodiment. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting.

The negative bias on the gate 60 (connected to WL terminal 70) and the positive voltage on bit line region 18 (connected to BL terminal 74) create a strong electric field (for example, about 10⁶V/cm in silicon, as described in Sze, p. 104) between the bit line region 18 and the floating body region 24 in the proximity of gate 60. This bends the energy band sharply upward near the gate 60 and bit line 18 junction overlap region, causing electrons to tunnel from the valence band of the bit line region 18 to the conduction band of the bit line region 18, leaving holes in the valence band. The electrons which tunnel across the energy band become the drain leakage current, while the holes are injected into floating body region 24 and become the hole charge that creates the logic-1 state.

FIG. 49 is a schematic illustration showing bias conditions for a write logic-0 operation performed on memory cell 250 according to an embodiment of the present invention. A write logic-0 operation can be performed by applying a negative voltage bias to the selected SL terminal 72, a zero voltage bias to the WL terminal 70, zero voltage bias to the BL terminal 74, zero or positive voltage bias to the CI terminal 86, and zero voltage bias to the substrate terminal 78; while zero voltage is applied to the unselected SL terminals 72, zero voltage is applied to the unselected BL terminals 74, zero voltage bias applied to the unselected WL terminals 70, zero or positive bias applied to the unselected CI terminals 86, and zero voltage bias applied to the substrate 78. Under these conditions, the p-n junction between floating body 24 and source line region 16 of the selected cell 250 is forward-biased, evacuating holes from the floating body 24. All memory cells 250 sharing the same selected SL terminal 72 will be written to simultaneously. To write arbitrary binary data to different memory cells 250, a write logic-0 operation is first performed on all the memory cells to be written, followed by one or more write logic-1 operations on the memory cells that must be written to logic-1.

In one particular non-limiting embodiment, about −1.2 volts is applied to selected SL terminal 72, about 0.0 volts is applied to WL terminal 70, about 0.0 volts is applied to BL terminal 74, about 0.0 volts or +1.2 volts is applied to CI terminal 86, and about 0.0 volts is applied to substrate terminal 78, while zero voltage is applied to the unselected SL terminals 72, zero voltage bias applied to the unselected WL terminals 70, zero or positive bias applied to the unselected CI terminal 86, zero voltage is applied to the unselected BL terminals 74 and zero voltage bias is applied to the substrate 78. These voltage levels are exemplary only may vary from embodiment to embodiment. Thus the exemplary embodiments, features, bias levels, etc., described are not limiting.

FIG. 50 is a schematic illustration showing bias conditions applied for a bit-selective write logic-0 operation performed on memory cell 250 according to an embodiment of the present invention. The bit-selective write logic-0 operation may be performed by applying a positive voltage to the selected WL terminal 70, a negative voltage to the selected BL terminal 74, zero voltage bias to the selected SL terminal 72, zero or positive voltage bias to the selected CI terminal 86, and a negative voltage to the selected substrate terminal 78; while zero voltage is applied to the unselected WL terminals 70, zero voltage is applied to the unselected BL terminals 74, zero voltage bias is applied to the unselected SL terminals 72, zero or positive voltage is applied to the unselected CI terminals 86, and zero voltage is applied to the unselected substrate terminals 78. Under these conditions, the floating body 24 potential will increase through capacitive coupling from the positive voltage applied to the WL terminal 70. As a result of the floating body 24 potential increase and the negative voltage applied to the BL terminal 74, the p-n junction between floating body region 24 and bit line region 18 is forward-biased, evacuating holes from the floating body 24.

To reduce undesired write logic-0 disturb to other memory cells 250 in a memory array, the applied potential can be optimized as follows: if the floating body 24 potential of state logic-1 is referred to as V_FB1, then the voltage applied to the WL terminal 70 is configured to increase the floating body 24 potential by V_FB1/2 while −V_FB1/2 is applied to BL terminal 74. Additionally, either ground or a slightly positive voltage may also be applied to the BL terminals 74 of unselected memory cells 250 that do not share the same BL terminal 74 as the selected memory cell 250a, while a negative voltage may also be applied to the WL terminals 70 of unselected memory cells 250 that do not share the same WL terminal 70 as the selected memory cell 250.

As illustrated in FIG. 50, the following exemplary bias conditions may be applied to the selected memory cell 50 to perform a bit-selective write logic-0 operation: a potential of about −0.2 volts to the selected BL terminal 74, a potential of about +1.2 volts to the selected WL terminal 70, about 0.0 volts is applied to the selected SL terminal 72, a potential of about +1.2 volts to the CI terminal 86, about −0.2 volts to the substrate terminal 78.

FIGS. 51 and 52A-52B illustrate a top-view and cross-sectional views, respectively, of an exemplary memory word 200, which comprises a plurality of memory cells 150 operating in a multi-time programmable mode according to another embodiment of the present invention. Two memory cells 150 are shown in the FIGS. 51 and 52A-52B. However, a memory word 200 may comprise one memory cell 150, or more than two memory cells 150, for example 16 memory cells 150.

As shown in FIG. 52A, memory cell 150 includes a substrate 12 of a first conductivity type such as p-type, for example (or, alternatively, n-type). Substrate 12 is typically made of silicon, but may also comprise, for example, germanium, silicon germanium, gallium arsenide, carbon nanotubes, and/or other semiconductor materials. In some embodiments of the invention, substrate 12 can be the bulk material of the semiconductor wafer. In another embodiment, as shown in FIG. 52B, substrate 12A of a first conductivity type (for example, p-type) can be a well of the first conductivity type embedded in a well 29 of the second conductivity type, such as n-type. The well 29 in turn can be another well inside substrate 12B of the first conductivity type (for example, p-type). In another embodiment, well 12A can be embedded inside the bulk of the semiconductor wafer of the second conductivity type (for example, n-type). These arrangements allow for segmentation of the substrate terminal, which is connected to region 12A. To simplify the description, the substrate 12 will usually be drawn as the semiconductor bulk material as it is in FIG. 51A.

Memory cell 150 also includes a buried layer region 22 of a second conductivity type, such as n-type, for example; a base region 24 of the first conductivity type, such as p-type, for example; and source/drain regions 16 and 18 of the second conductivity type, such as n-type, for example.

The base region 24 is common for all memory cells 150 in the memory word 200. The base region 24 of the first conductivity type is bounded on top by source line region 16, drain region 18, well-tap region 19, and insulating layer 62 (or by surface 14 in general), on the bottom by buried layer 22, and by insulating layer 26 at the edge of the memory word 200. Base region 24 may be the portion of the original substrate 12 above buried layer 22 if buried layer 22 is implanted. Alternatively, base region 24 may be epitaxially grown. Depending on how buried layer 22 and the base region 24 are formed, base region 24 may have the same doping as substrate 12 in some embodiments or a different doping, if desired in other embodiments.

A source line region 16 having a second conductivity type, such as n-type, for example, is provided in base region 24, so as to bound a portion of the top of the floating body region in a manner discussed above, and is exposed at surface 14. Source line region 16 may be formed by an implantation process on the material making up substrate 12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion or a selective epitaxial growth process could be used to form source line region 16.

A bit line region 18, also referred to as drain region 18, having a second conductivity type, such as n-type, for example, is also provided in base region 24, so as to bound a portion of the top of the floating body region in a manner discussed above, and is exposed at cell surface 14. Bit line region 18 may be formed by an implantation process on the material making up substrate 12, according to any implantation process known and typically used in the art. Alternatively, a solid state diffusion or a selective epitaxial growth process could be used to form bit line region 18.

A gate 60 is positioned in between the source line region 16 and the drain region 18, above the base region 24. The gate 60 is insulated from the base region 24 by a dielectric layer 62. Dielectric layer 62 may be made of silicon oxide and/or other dielectric materials, including high-K dielectric materials, such as, but not limited to, tantalum peroxide, titanium oxide, zirconium oxide, hafnium oxide, and/or aluminum oxide. The gate 60 may be made of, for example, polysilicon material or metal gate electrode, such as tungsten, tantalum, titanium and their nitrides.

Cell 150 includes several terminals: word line (WL) terminal 70 electrically connected to gate 60, bit line (BL) terminal 74 electrically connected to bit line region 18, source line (SL) terminal 72 electrically connected to source line region 16, buried well (BW) terminal 76 electrically connected to buried layer 22, and substrate terminal 78 electrically connected to the substrate 12. Alternatively, the SL terminal 72 may be electrically connected to region 18 and BL terminal 74 may be electrically connected to region 16.

Memory word 200 also comprises a well-tap region 19 of first conductivity type, such as p-type, which is electrically connected to the well-tap (WELL) terminal 75.

The write logic-1 operation of the memory cell 150 is performed by inducing a soft breakdown of the gate dielectric layer 62. The write operation may be performed for example by applying the following bias conditions: a positive voltage to the gate electrode 60, a negative voltage to the base region 24 (through the WELL terminal 75), floating or zero voltage to both source and drain regions 16 and 18, and zero or positive voltage to the BW terminal 76, and zero voltage is applied to the substrate terminal 78.

In one particular non-limiting embodiment, about +3.0 volts is applied to the selected WL terminal 70, about −1.0 volts is applied to the WELL terminal 75, about 0.0 volts is applied to terminal SL 72, about 0.0 volts is applied to the selected BL terminal 74, about +1.2 volts is applied to terminal 76, and about 0.0 volts is applied to substrate terminal 78.

The read operation is performed by applying the following bias conditions: a positive voltage is applied to the selected WL terminal 70, a positive voltage is applied to the selected BL terminal 74, zero voltage is applied to the SL terminal 72, a positive voltage is applied to the BW terminal 76, zero voltage is applied to the substrate terminal 78, while WELL terminal 75 is left floating. A higher gate leakage current will flow from the gate 60 to the base region 24 when soft breakdown has happened on gate dielectric 62 compared to if the gate dielectric 62 has not had a soft breakdown.

FIG. 52C illustrates an equivalent circuit representation of the memory cell 150, which illustrates a bipolar device 130. The base current (from the gate 60) will be amplified by the bipolar device 130. As a result, a high current may be observed flowing from the BL terminal 74 to the SL terminal 72, which may be used to determine the state of the memory cell 150. A memory cell 150 where the gate dielectric 62 has had a soft breakdown will conduct a higher current (from the BL terminal 74 to the SL terminal 72). As a result, only a soft breakdown is needed, in contrast to the irreversible hard breakdown used in one-time programmable memory cell, for example as described in U.S. Pat. No. 6,667,902 to Jack Zezhong Peng, titled “Semiconductor memory cell and memory array using a breakdown phenomena in an ultra-thin dielectric” and U.S. Pat. No. 7,402,855 to Wlodek Kurjanowicz, titled “Split-Channel Antifuse Array Architecture”, both of which are hereby incorporated herein, in their entireties, by reference thereto. The voltage applied to the selected WL terminal 70 may be less than the threshold voltage of the memory cell 150 to reduce the current flow from the channel region near the surface 14.

In one particular non-limiting embodiment, about +0.4 volts is applied to the selected WL terminal 70, about 0.0 volts is applied to terminal SL 72, about +1.2 volts is applied to the selected BL terminal 74, about +1.2 volts is applied to terminal 76, and about 0.0 volts is applied to terminal 78, while WELL terminal 75 is left floating.

The write logic-1 operation may also be performed by first applying a positive voltage applied to the WL terminal 70, followed by a measurement of the bipolar current from the BL terminal 74 to the SL terminal 72, referred as verification process. If the soft breakdown is not observed yet, a higher voltage is applied to the WL terminal 70, followed by another verification process. Once the target bipolar current level is reached, the write operation is terminated. Because the WL voltage is applied gradually, this avoids the undesired hard breakdown of the gate dielectric 62.

The soft breakdown can be recovered by applying a voltage with opposite polarity as the write operation. This operation (which will be referred to as a reset operation or write logic-0 operation) may be performed by applying the following bias conditions: a negative voltage is applied to the selected WL terminal 70, zero voltage is applied to the selected WELL terminal 75, floating or zero voltage is applied to both source and drain regions 16 and 18, zero or positive voltage is applied to the BW terminal 76, and zero voltage is applied to the substrate terminal 78.

Memory cells 150 will still function under soft breakdown condition (in contrast to the hard breakdown of the gate dielectric 62, which effectively short the gate electrode 60 to the base region 24). As a result, the reset and write operations may be performed multiple times to the memory cells 150 and memory cells 150 may operate as multi time programmable memory device.

In order to reduce the effect of a neighboring cell, the read operation may be limited to only one selected memory cell 150 for each memory word 200.

From the foregoing it can be seen that a memory cell having an electrically floating body has been described. While the foregoing written description of the invention enables one of ordinary skill to make and use what is considered presently to be the best mode thereof, those of ordinary skill will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiment, method, and examples herein. The invention should therefore not be limited by the above described embodiment, method, and examples, but by all embodiments and methods within the scope and spirit of the invention as claimed.

Claims

1. A semiconductor memory instance comprising: an array of semiconductor memory cells, the array comprising at least two memory sub-arrays, each memory sub-array comprising:a plurality of said semiconductor memory cells arranged in at least one column and at least one row, wherein at least two of said semiconductor memory cells each include: a floating body region configured to be charged to a level indicative of a state of the memory cell;a buried well region contacting said floating body regions of said at least two of said semiconductor memory cells, wherein said buried well region is common to said at least two of said semiconductor memory cells in one of said memory sub-arrays;wherein when a first semiconductor memory cell of said at least two of said semiconductor memory cells is in a first state and a second semiconductor memory cell of said at least two of said semiconductor memory cells is in a second state, application of a bias applied through said buried well region maintains said first semiconductor memory cell in said first state and said second semiconductor memory cell in said second state;a first decoder circuit configured to select at least one of said at least one column or at least one of said at least one row;a second decoder circuit configured to select at least one of said memory sub-arrays; andwherein said buried well region may be set to a first bias condition during a first memory operation and to a second bias condition during a second memory operation.
2. The semiconductor memory instance of claim 1, wherein said second decoder circuit is configured to selectively disable at least one of said at least two memory sub-arrays.
3. The semiconductor memory instance of claim 1, wherein said second decoder circuit is configured to apply a bias to first and second collectors of said at least two of said semiconductor memory cells within one of said at least two memory sub-arrays to maintain states of said at least two semiconductor memory cells in said one of said at least two memory sub-arrays during a high portion of a clock cycle and to turn off said bias during a low portion of the clock cycle.
4. The semiconductor memory instance of claim 1, wherein each said semiconductor memory cell is configured to provide at least two stable states.
5. The semiconductor memory instance of claim 1, comprising a fin structure extending from a substrate.
6. The semiconductor memory instance of claim 1, further comprising an address signal as an input to said second decoder circuit to select said at least one of said memory sub-arrays.
7. The semiconductor memory instance of claim 1, wherein said second decoder circuit is configured to remove a bias to one or more of said memory sub-arrays, while maintaining said bias to at least one other of said memory sub-arrays.
8. The semiconductor memory instance of claim 1, further comprising a signal generator circuit to provide bias conditions for operations of said semiconductor memory instance.
9. The semiconductor memory instance of claim 8, wherein said signal generator circuit provides different ramp rates for read and write operations.
10. The semiconductor instance of claim 9, wherein said ramp rates for said read operations are lower than said ramp rates for said write operations.
11. A semiconductor memory instance comprising: an array of semiconductor memory cells, the array comprising at least two memory sub-arrays, each memory sub-array comprising:a plurality of said semiconductor memory cells arranged in at least one column and at least one row, wherein at least two of said semiconductor memory cells each include: a floating body region configured to be charged to a level indicative of a state of the memory cell;a buried well region contacting said floating body regions of said at least two of said semiconductor memory cells, wherein said buried well region is common to said at least two of said semiconductor memory cells in one of said memory sub-arrays;wherein when a first semiconductor memory cell of said at least two of said semiconductor memory cells is in a first state and a second semiconductor memory cell of said at least two of said semiconductor memory cells is in a second state, application of a bias applied through said buried well region maintains said first semiconductor memory cell in said first state and said second semiconductor memory cell in said second state;wherein said states of said semiconductor memory cells are maintained upon repeated read operations;a first decoder circuit configured to select at least one of said at least one column or at least one of said at least one row;a second decoder circuit configured to select at least one of said at least two memory sub-arrays; andwherein said buried well region may be set to a first bias condition during a first memory operation and to a second bias condition during a second memory operation.
12. The semiconductor memory instance of claim 11, wherein said second decoder circuit is configured to selectively disable at least one of said at least two memory sub-arrays.
13. The semiconductor memory instance of claim 11, wherein said second decoder circuit is configured to apply a bias to at least first and second collectors of first and second semiconductor memory cells, respectively, of said at least two semiconductor memory cells within one of said at least two memory sub-arrays to maintain states of said at least first and second semiconductor memory cells of said at least two of said semiconductor memory cells in said one of said at least two memory sub-arrays during a high portion of a clock cycle and to turn off said bias during a low portion of the clock cycle.
14. The semiconductor memory instance of claim 11, wherein each said semiconductor memory cell is configured to provide at least two stable states.
15. The semiconductor memory instance of claim 11, comprising a fin structure extending from a substrate.
16. The semiconductor memory instance of claim 11, further comprising an address signal as an input to said second decoder circuit to select said at least one of said memory sub-arrays.
17. The semiconductor memory instance of claim 11, wherein said second decoder circuit is configured to remove a bias to one or more of said at least one of said memory sub-arrays, while maintaining said bias to at least one other of said at least two memory sub-arrays.
18. The semiconductor memory instance of claim 11, further comprising a signal generator circuit to provide bias conditions for operations of said semiconductor memory instance.
19. The semiconductor memory instance of claim 18, wherein said signal generator circuit provides different ramp rates for read and write operations.
20. The semiconductor instance of claim 19, wherein said ramp rates for said read operations are lower than said ramp rates for said write operations.

CROSS-REFERENCE

This application is a continuation of co-pending U.S. application Ser. No. 17/569,417, filed Jan. 5, 2022, which is a continuation of U.S. application Ser. No. 17/161,403, filed Jan. 28, 2021, now U.S. Pat. No. 11,250,905, which is a continuation of U.S. application Ser. No. 16/776,160, filed Jan. 29, 2020, now U.S. Pat. No. 10,923,183, which is a division of U.S. application Ser. No. 16/144,544, filed Sep. 27, 2018, now U.S. Pat. No. 10,580,482, which is a continuation of U.S. application Ser. No. 15/712,041, filed Sep. 21, 2017, now U.S. Pat. No. 10,115,451, which is a division of U.S. application Ser. No. 15/287,903, filed Oct. 7, 2016, now U.S. Pat. No. 9,799,392, which is a continuation of U.S. application Ser. No. 14/825,628, filed Aug. 13, 2015, now U.S. Pat. No. 9,496,053, which claims the benefit of U.S. Provisional Application Nos. 62/038,188, filed Aug. 15, 2014; 62/051,759, filed Sep. 17, 2014; and 62/058,892, filed Oct. 2, 2014, each of which applications and patents are hereby incorporated herein, in their entireties, by reference thereto and to which applications we claim priority.

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Related Publications (1)

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62058892	Oct 2014	US
62051759	Sep 2014	US
62038188	Aug 2014	US

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Parent	16144544	Sep 2018	US
Child	16776160		US
Parent	15287903	Oct 2016	US
Child	15712041		US

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Parent	17569417	Jan 2022	US
Child	18205530		US
Parent	17161403	Jan 2021	US
Child	17569417		US
Parent	16776160	Jan 2020	US
Child	17161403		US
Parent	15712041	Sep 2017	US
Child	16144544		US
Parent	14825268	Aug 2015	US
Child	15287903		US

Memory device comprising electrically floating body transistor

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