Nick Kepler

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Resist trim process to define small openings in dielectric layers
- Patent number 7,737,021
- Issue date Jun 15, 2010
- Globalfoundries Inc.
- Srikanteswara Dakshina-Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Minimizing transistor size in integrated circuits
- Patent number 7,026,691
- Issue date Apr 11, 2006
- Advanced Micro Devices, Inc.
- Craig S. Sander
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow trench isolation formation with ion implantation
- Patent number 6,599,810
- Issue date Jul 29, 2003
- Advanced Micro Devices, Inc.
- Nick Kepler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and test structure for characterizing sidewall damage in a s...
- Patent number 6,600,333
- Issue date Jul 29, 2003
- Advanced Micro Devices, Inc.
- Jeremy I. Martin
- G01 - MEASURING TESTING
Information Patent Grant
Sidewall treatment for low dielectric constant (low K) materials by...
- Patent number 6,514,844
- Issue date Feb 4, 2003
- Advanced Micro Devices, Inc.
- Jeremy I. Martin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Resist trim process to define small openings in dielectric layers
- Patent number 6,500,755
- Issue date Dec 31, 2002
- Advanced Micro Devices, Inc.
- Srikanteswara Dakshina-Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of defining small openings in dielectric layers
- Patent number 6,406,993
- Issue date Jun 18, 2002
- Advanced Micro Devices, Inc.
- Srikanteswara Dakshina-Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming junction-leakage free metal salicide in a semicon...
- Patent number 6,383,906
- Issue date May 7, 2002
- Advanced Micro Devices, Inc.
- Karsten Wieczorek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Prevention of dopant out-diffusion during silicidation and junction...
- Patent number 6,380,040
- Issue date Apr 30, 2002
- Advanced Micro Devices, Inc.
- Nick Kepler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow trench isolation formation with two source/drain masks and...
- Patent number 6,380,047
- Issue date Apr 30, 2002
- Advanced Micro Devices, Inc.
- Basab Bandyopadhyay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device with partial passivation layer
- Patent number 6,313,538
- Issue date Nov 6, 2001
- Advanced Micro Devices, Inc.
- Christian Zistl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Minimizing transistor size in integrated circuits
- Patent number 6,287,953
- Issue date Sep 11, 2001
- Advanced Micro Devices, Inc.
- Craig S. Sander
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming junction-leakage free metal silicide in a semicon...
- Patent number 6,274,511
- Issue date Aug 14, 2001
- Advanced Micro Devices, Inc.
- Karsten Wieczorek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a semiconductor device with metal silicide regions
- Patent number 6,268,255
- Issue date Jul 31, 2001
- Advanced Micro Devices, Inc.
- Paul R. Besser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming junction-leakage free metal silicide in a semicon...
- Patent number 6,255,214
- Issue date Jul 3, 2001
- Advanced Micro Devices, Inc.
- Karsten Wieczorek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of junctions by diffusion from a doped film at silicidation
- Patent number 6,238,986
- Issue date May 29, 2001
- Advanced Micro Devices, Inc.
- Nick Kepler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stepper alignment mark structure for maintaining alignment integrity
- Patent number 6,239,031
- Issue date May 29, 2001
- Advanced Micro Devices, Inc.
- Nick Kepler
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method of forming junction leakage free metal silicide in a semicon...
- Patent number 6,204,177
- Issue date Mar 20, 2001
- Advanced Micro Devices, Inc.
- Paul R. Besser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming minimal size spaces in integrated circuit conductive lines
- Patent number 6,191,034
- Issue date Feb 20, 2001
- Advanced Micro Devices
- Richard K. Klein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow trench isolation formation without planarization mask
- Patent number 6,171,962
- Issue date Jan 9, 2001
- Advanced Micro Devices, Inc.
- Olov Karlsson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of junctions by diffusion from a doped amorphous silicon...
- Patent number 6,169,005
- Issue date Jan 2, 2001
- Advanced Micro Devices, Inc.
- Nick Kepler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming ultra-shallow junctions in a semiconductor wafer...
- Patent number 6,165,903
- Issue date Dec 26, 2000
- Advanced Micro Devices, Inc.
- Paul R. Besser
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-depth junction formation tailored to silicide formation
- Patent number 6,162,689
- Issue date Dec 19, 2000
- Advanced Micro Devices, Inc.
- Nick Kepler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for generating limited isolation trench width structures and...
- Patent number 6,162,699
- Issue date Dec 19, 2000
- Advanced Micro Devices, Inc.
- Larry Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for decreasing the contact resistance of silicide contacts b...
- Patent number 6,156,615
- Issue date Dec 5, 2000
- Advanced Micro Devices, Inc.
- Nick Kepler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow junction formation by out-diffusion from a doped dielectric...
- Patent number 6,150,243
- Issue date Nov 21, 2000
- Advanced Micro Devices, Inc.
- Karsten Wieczorek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Minimizing transistor size in integrated circuits
- Patent number 6,146,954
- Issue date Nov 14, 2000
- Advanced Micro Devices, Inc.
- Richard K. Klein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow trench isolation formation with spacer-assisted ion implant...
- Patent number 6,143,624
- Issue date Nov 7, 2000
- Advanced Micro Devices, Inc.
- Nick Kepler
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow trench isolation with spacers for improved gate oxide quality
- Patent number 6,130,467
- Issue date Oct 10, 2000
- Advanced Micro Devices, Inc.
- Basab Bandyopadhyay
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Shallow trench isolation formation with simplified reverse planariz...
- Patent number 6,124,183
- Issue date Sep 26, 2000
- Advanced Micro Devices, Inc.
- Olov Karlsson
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Resist trim process to define small openings in dielectric layers
- Publication number 20020068436
- Publication date Jun 6, 2002
- Srikanteswara Dakshina-Murthy
- H01 - BASIC ELECTRIC ELEMENTS

Nick Kepler

Person

Patents Grantslast 30 patents

Resist trim process to define small openings in dielectric layers

Minimizing transistor size in integrated circuits

Shallow trench isolation formation with ion implantation

Method and test structure for characterizing sidewall damage in a s...

Sidewall treatment for low dielectric constant (low K) materials by...

Resist trim process to define small openings in dielectric layers

Method of defining small openings in dielectric layers

Method of forming junction-leakage free metal salicide in a semicon...

Prevention of dopant out-diffusion during silicidation and junction...

Shallow trench isolation formation with two source/drain masks and...

Semiconductor device with partial passivation layer

Minimizing transistor size in integrated circuits

Method of forming junction-leakage free metal silicide in a semicon...

Method of forming a semiconductor device with metal silicide regions

Method of forming junction-leakage free metal silicide in a semicon...

Formation of junctions by diffusion from a doped film at silicidation

Stepper alignment mark structure for maintaining alignment integrity

Method of forming junction leakage free metal silicide in a semicon...

Forming minimal size spaces in integrated circuit conductive lines

Shallow trench isolation formation without planarization mask

Formation of junctions by diffusion from a doped amorphous silicon...

Method of forming ultra-shallow junctions in a semiconductor wafer...

Multi-depth junction formation tailored to silicide formation

Method for generating limited isolation trench width structures and...

Method for decreasing the contact resistance of silicide contacts b...

Shallow junction formation by out-diffusion from a doped dielectric...

Minimizing transistor size in integrated circuits

Shallow trench isolation formation with spacer-assisted ion implant...

Shallow trench isolation with spacers for improved gate oxide quality

Shallow trench isolation formation with simplified reverse planariz...

Patents Applicationslast 30 patents

Resist trim process to define small openings in dielectric layers