Claims
- 1. A method of manufacturing a semiconductor device, which method comprises:etching to form a set of alignment marks on a main surface of a semiconductor substrate, the alignment marks comprising a plurality of first sections each having an upper surface substantially flush with the main surface and second sections separating the plurality of first sections, each second section comprising a plurality of first trenches spaced apart by first uprights having an upper surface substantially flush with the main surface; depositing a substantially transparent layer on the set of alignment marks; and planarizing such that the substantially transparent layer has a substantially planar upper surface over the set of alignment marks after planarizing.
- 2. The method according to claim 1, further comprising:etching to form a dummy topographical area on the main surface peripheral to and extending away from the set of alignment marks a distance, comprising a plurality of second trenches spaced apart by second uprights having an upper surface substantially flush with the main surface; and depositing the substantially transparent layer on the dummy topographical area.
- 3. A method of manufacturing a semiconductor device, which method comprises:forming a set of alignment marks on a main surface of a semiconductor substrate; etching to form a dummy topographical area on the main surface peripheral to and extending away from the set of alignment marks a distance, comprising a plurality of second trenches spaced apart by second uprights having an upper surface substantially flush with the main surface; depositing a substantially transparent layer on the set of alignment marks and on the dummy topographical area; and planarizing such that the substantially transparent layer has a substantially planar upper surface over the set of alignment marks after planarizing.
Parent Case Info
This application is a divisional of application Ser. No. 09/184,861 filed Nov. 3, 1998 now U.S. Pat. No. 6,037,671.
US Referenced Citations (6)