Ning Cheng

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods and apparatus for reducing reliability degradation on an in...
- Patent number 11,113,442
- Issue date Sep 7, 2021
- Intel Corporation
- Ning Cheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Manufacture of interconnects for integration of multiple integrated...
- Patent number 10,541,205
- Issue date Jan 21, 2020
- Intel Corporation
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and apparatuses for optimizing power and functionality in t...
- Patent number 10,037,992
- Issue date Jul 31, 2018
- Altera Corporation
- Zhiyuan Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable integrated circuits with in-operation reconfiguration...
- Patent number 9,984,734
- Issue date May 29, 2018
- Altera Corporation
- Andy L. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods for fabricating integrated circuits with triple gate oxide...
- Patent number 9,892,922
- Issue date Feb 13, 2018
- Altera Corporation
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable integrated circuits with in-operation reconfiguration...
- Patent number 9,607,671
- Issue date Mar 28, 2017
- Altera Corporation
- Andy L. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
HTO offset for long leffective, better device performance
- Patent number 9,455,352
- Issue date Sep 27, 2016
- Cypress Semiconductor Corporation
- Ning Cheng
- G11 - INFORMATION STORAGE
Information Patent Grant
Power and die size optimization in FinFETs
- Patent number 9,397,095
- Issue date Jul 19, 2016
- Altera Corporation
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Programmable integrated circuits with in-operation reconfiguration...
- Patent number 9,299,396
- Issue date Mar 29, 2016
- Altera Corporation
- Andy L. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Oro and orpro with bit line trench to suppress transport program di...
- Patent number 9,245,895
- Issue date Jan 26, 2016
- Cypress Semiconductor Corporation
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming spaced-apart charge trapping stacks
- Patent number 9,224,748
- Issue date Dec 29, 2015
- Cypress Semiconductor Corporation
- Hiroyuki Kinoshita
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High-k dielectric device and process
- Patent number 9,166,045
- Issue date Oct 20, 2015
- Altera Coporation
- Che Ta Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metal routing in advanced process technologies
- Patent number 9,099,531
- Issue date Aug 4, 2015
- Altera Corporation
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High-k dielectric device and process
- Patent number 8,835,265
- Issue date Sep 16, 2014
- Altera Corporation
- Che Ta Hsu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flash memory devices and methods for fabricating same
- Patent number 8,748,972
- Issue date Jun 10, 2014
- Spansion LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High ultraviolet light absorbance silicon oxynitride film for impro...
- Patent number 8,735,960
- Issue date May 27, 2014
- Spansion LLC
- Minh Q. Tran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
HTO offset for long Leffective, better device performance
- Patent number 8,653,581
- Issue date Feb 18, 2014
- Spansion LLC
- Ning Cheng
- G11 - INFORMATION STORAGE
Information Patent Grant
Flash memory devices and methods for fabricating the same
- Patent number 8,486,782
- Issue date Jul 16, 2013
- Spansion LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selective silicide formation using resist etch back
- Patent number 8,445,372
- Issue date May 21, 2013
- Spansion LLC
- Kyunghoon Min
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
HTO offset and BL trench process for memory device to improve devic...
- Patent number 8,330,209
- Issue date Dec 11, 2012
- Spansion LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ultraviolet radiation blocking interlayer dielectric
- Patent number 8,022,468
- Issue date Sep 20, 2011
- Spansion LLC
- Minh Van Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
ORO and ORPRO with bit line trench to suppress transport program di...
- Patent number 8,012,830
- Issue date Sep 6, 2011
- Spansion LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit contact system
- Patent number 7,994,047
- Issue date Aug 9, 2011
- Spansion LLC
- Christy Mei-Chu Woo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
HTO offset spacers and dip off process to define junction
- Patent number 7,943,983
- Issue date May 17, 2011
- Spansion LLC
- Huaqiang Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
HTO offset and BL trench process for memory device to improve devic...
- Patent number 7,935,596
- Issue date May 3, 2011
- Spansion LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Film stacks to prevent UV-induced device damage
- Patent number 7,927,723
- Issue date Apr 19, 2011
- Spansion LLC
- Angela T. Hui
- G02 - OPTICS
Information Patent Grant
Use of a polymer spacer and Si trench in a bitline junction of a fl...
- Patent number 7,906,807
- Issue date Mar 15, 2011
- Spansion LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Split charge storage node inner spacer process
- Patent number 7,829,936
- Issue date Nov 9, 2010
- Spansion LLC
- Minghao Shen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual storage node memory devices and methods for fabricating the same
- Patent number 7,785,965
- Issue date Aug 31, 2010
- Spansion LLC
- Unsoon Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Use of a polymer spacer and Si trench in a bitline junction of a fl...
- Patent number 7,776,688
- Issue date Aug 17, 2010
- Spansion LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METHODS AND APPARATUS FOR REDUCING RELIABILITY DEGRADATION ON AN IN...
- Publication number 20210383049
- Publication date Dec 9, 2021
- Intel Corporation
- Ning Cheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR REDUCING RELIABILITY DEGRADATION ON AN IN...
- Publication number 20190095571
- Publication date Mar 28, 2019
- Intel Corporation
- Ning Cheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE INTEGRATED CIRCUITS WITH IN-OPERATION RECONFIGURATION...
- Publication number 20170200484
- Publication date Jul 13, 2017
- Altera Corporation
- Andy L. Lee
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH PERFORMANCE FINFET
- Publication number 20150206965
- Publication date Jul 23, 2015
- Altera Corporation
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HTO OFFSET FOR LONG LEFFECTIVE, BETTER DEVICE PERFORMANCE
- Publication number 20140167138
- Publication date Jun 19, 2014
- SPANSION LLC
- Ning Cheng
- G11 - INFORMATION STORAGE
Information Patent Application
FLASH MEMORY DEVICES AND METHODS FOR FABRICATING SAME
- Publication number 20130277733
- Publication date Oct 24, 2013
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ORO AND ORPRO WITH BIT LINE TRENCH TO SUPPRESS TRANSPORT PROGRAM DI...
- Publication number 20110278660
- Publication date Nov 17, 2011
- SPANSION LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HTO OFFSET AND BL TRENCH PROCESS FOR MEMORY DEVICE TO IMPROVE DEVIC...
- Publication number 20110169069
- Publication date Jul 14, 2011
- SPANSION, LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FL...
- Publication number 20100264480
- Publication date Oct 21, 2010
- SPANSION LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING SPACED-APART CHARGE TRAPPING STACKS
- Publication number 20100187597
- Publication date Jul 29, 2010
- Hiroyuki Kinoshita
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HTO OFFSET SPACERS AND DIP OFF PROCESS TO DEFINE JUNCTION
- Publication number 20100155785
- Publication date Jun 24, 2010
- SPANSION LLC
- Huaqiang Wu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HTO OFFSET AND BL TRENCH PROCESS FOR MEMORY DEVICE TO IMPROVE DEVIC...
- Publication number 20100155816
- Publication date Jun 24, 2010
- SPANSION LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HTO OFFSET FOR LONG LEFFECTIVE, BETTER DEVICE PERFORMANCE
- Publication number 20100155817
- Publication date Jun 24, 2010
- SPANSION LLC
- Ning Cheng
- G11 - INFORMATION STORAGE
Information Patent Application
High ultraviolet light absorbance silicon oxynitride film for impro...
- Publication number 20100123178
- Publication date May 20, 2010
- Minh Q. Tran
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE SILICIDE FORMATION USING RESIST ETCH BACK
- Publication number 20100099249
- Publication date Apr 22, 2010
- SPANSION LLC
- Kyunghoon Min
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELECTIVE SILICIDE FORMATION USING RESIST ETCHBACK
- Publication number 20090111265
- Publication date Apr 30, 2009
- SPANSION LLC
- Kyunghoon Min
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SPLIT CHARGE STORAGE NODE INNER SPACER PROCESS
- Publication number 20090101963
- Publication date Apr 23, 2009
- SPANSION LLC
- Minghao Shen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FL...
- Publication number 20090042378
- Publication date Feb 12, 2009
- SPANSION LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ORO AND ORPRO WITH BIT LINE TRENCH TO SUPPRESS TRANSPORT PROGRAM DI...
- Publication number 20090039405
- Publication date Feb 12, 2009
- SPANSION LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL BIT FLASH MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME
- Publication number 20080169502
- Publication date Jul 17, 2008
- Amol Ramesh Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FABRICATING A MEMORY DEVICE INCLUDING A DUAL BIT MEMORY...
- Publication number 20080153228
- Publication date Jun 26, 2008
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME
- Publication number 20080149988
- Publication date Jun 26, 2008
- Hiroyuki Kinoshita
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLASH MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME
- Publication number 20080153236
- Publication date Jun 26, 2008
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLASH MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME
- Publication number 20080149989
- Publication date Jun 26, 2008
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL BIT FLASH MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME
- Publication number 20080079062
- Publication date Apr 3, 2008
- Amol Ramesh Joshi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL STORAGE NODE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME
- Publication number 20080064165
- Publication date Mar 13, 2008
- Unsoon Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Contact spacer formation using atomic layer deposition
- Publication number 20070077754
- Publication date Apr 5, 2007
- Minh Van Ngo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to impr...
- Publication number 20070029604
- Publication date Feb 8, 2007
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device and method of fabricating the same
- Publication number 20060214218
- Publication date Sep 28, 2006
- Kiyokazu Shishido
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming narrowly spaced flash memory contact openings and...
- Publication number 20060035459
- Publication date Feb 16, 2006
- Emmanuil H. Lingunis
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Person

Patents Grantslast 30 patents

Methods and apparatus for reducing reliability degradation on an in...

Manufacture of interconnects for integration of multiple integrated...

Methods and apparatuses for optimizing power and functionality in t...

Programmable integrated circuits with in-operation reconfiguration...

Methods for fabricating integrated circuits with triple gate oxide...

Programmable integrated circuits with in-operation reconfiguration...

HTO offset for long leffective, better device performance

Power and die size optimization in FinFETs

Programmable integrated circuits with in-operation reconfiguration...

Oro and orpro with bit line trench to suppress transport program di...

Method of forming spaced-apart charge trapping stacks

High-k dielectric device and process

Metal routing in advanced process technologies

High-k dielectric device and process

Flash memory devices and methods for fabricating same

High ultraviolet light absorbance silicon oxynitride film for impro...

HTO offset for long Leffective, better device performance

Flash memory devices and methods for fabricating the same

Selective silicide formation using resist etch back

HTO offset and BL trench process for memory device to improve devic...

Ultraviolet radiation blocking interlayer dielectric

ORO and ORPRO with bit line trench to suppress transport program di...

Integrated circuit contact system

HTO offset spacers and dip off process to define junction

HTO offset and BL trench process for memory device to improve devic...

Film stacks to prevent UV-induced device damage

Use of a polymer spacer and Si trench in a bitline junction of a fl...

Split charge storage node inner spacer process

Dual storage node memory devices and methods for fabricating the same

Use of a polymer spacer and Si trench in a bitline junction of a fl...

Patents Applicationslast 30 patents

METHODS AND APPARATUS FOR REDUCING RELIABILITY DEGRADATION ON AN IN...

METHODS AND APPARATUS FOR REDUCING RELIABILITY DEGRADATION ON AN IN...

PROGRAMMABLE INTEGRATED CIRCUITS WITH IN-OPERATION RECONFIGURATION...

HIGH PERFORMANCE FINFET

HTO OFFSET FOR LONG LEFFECTIVE, BETTER DEVICE PERFORMANCE

FLASH MEMORY DEVICES AND METHODS FOR FABRICATING SAME

ORO AND ORPRO WITH BIT LINE TRENCH TO SUPPRESS TRANSPORT PROGRAM DI...

HTO OFFSET AND BL TRENCH PROCESS FOR MEMORY DEVICE TO IMPROVE DEVIC...

USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FL...

METHOD OF FORMING SPACED-APART CHARGE TRAPPING STACKS

HTO OFFSET SPACERS AND DIP OFF PROCESS TO DEFINE JUNCTION

HTO OFFSET AND BL TRENCH PROCESS FOR MEMORY DEVICE TO IMPROVE DEVIC...

HTO OFFSET FOR LONG LEFFECTIVE, BETTER DEVICE PERFORMANCE

High ultraviolet light absorbance silicon oxynitride film for impro...

SELECTIVE SILICIDE FORMATION USING RESIST ETCH BACK

SELECTIVE SILICIDE FORMATION USING RESIST ETCHBACK

SPLIT CHARGE STORAGE NODE INNER SPACER PROCESS

USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FL...

ORO AND ORPRO WITH BIT LINE TRENCH TO SUPPRESS TRANSPORT PROGRAM DI...

DUAL BIT FLASH MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME

METHODS FOR FABRICATING A MEMORY DEVICE INCLUDING A DUAL BIT MEMORY...

SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME

FLASH MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME

FLASH MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME

DUAL BIT FLASH MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME

DUAL STORAGE NODE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME

Contact spacer formation using atomic layer deposition

Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to impr...

Semiconductor device and method of fabricating the same

Method of forming narrowly spaced flash memory contact openings and...