Ohsang Kwon

Person

San Diego, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Layout construction for addressing electromigration
- Patent number 11,508,725
- Issue date Nov 22, 2022
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layout construction for addressing electromigration
- Patent number 11,437,375
- Issue date Sep 6, 2022
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layout construction for addressing electromigration
- Patent number 10,600,785
- Issue date Mar 24, 2020
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Standard cell architecture with M1 layer unidirectional routing
- Patent number 10,593,700
- Issue date Mar 17, 2020
- QUALCOMM Incorporated
- Mukul Gupta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layout construction for addressing electromigration
- Patent number 10,580,774
- Issue date Mar 3, 2020
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hybrid coloring methodology for multi-pattern technology
- Patent number 10,175,571
- Issue date Jan 8, 2019
- QUALCOMM Incorporated
- Xiangdong Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout construction for addressing electromigration
- Patent number 10,074,609
- Issue date Sep 11, 2018
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layout construction for addressing electromigration
- Patent number 9,972,624
- Issue date May 15, 2018
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Standard cell architecture with M1 layer unidirectional routing
- Patent number 9,887,209
- Issue date Feb 6, 2018
- QUALCOMM Incorporated
- Mukul Gupta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Layout construction for addressing electromigration
- Patent number 9,786,663
- Issue date Oct 10, 2017
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Voltage comparator
- Patent number 9,685,940
- Issue date Jun 20, 2017
- QUALCOMM Incorporated
- Ramaprasath Vilangudipitchai
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Layout construction for addressing electromigration
- Patent number 9,659,936
- Issue date May 23, 2017
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Cross-couple in multi-height sequential cells for uni-directional M1
- Patent number 9,640,480
- Issue date May 2, 2017
- QUALCOMM Incorporated
- Mukul Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Grounding dummy gate in scaled layout design
- Patent number 9,379,058
- Issue date Jun 28, 2016
- QUALCOMM Incorporated
- Stanley Seungchul Song
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SOC design with critical technology pitch alignment
- Patent number 9,331,016
- Issue date May 3, 2016
- QUALCOMM Incorporated
- Xiangdong Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High performance standard cell with continuous oxide definition and...
- Patent number 9,318,476
- Issue date Apr 19, 2016
- QUALCOMM Incorporated
- Xiangdong Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Continuous diffusion configurable standard cell architecture
- Patent number 9,306,570
- Issue date Apr 5, 2016
- QUALCOMM Incorporated
- Satyanarayana Sahu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital circuit design with semi-continuous diffusion standard cell
- Patent number 9,190,405
- Issue date Nov 17, 2015
- QUALCOMM Incorporated
- Xiangdong Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High frequency synchronizer
- Patent number 9,020,084
- Issue date Apr 28, 2015
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Latch-based array with enhanced read enable fault testing
- Patent number 8,971,098
- Issue date Mar 3, 2015
- QUALCOMM Incorporated
- Gaurav Bhargava
- G11 - INFORMATION STORAGE
Information Patent Grant
Latch-based array with robust design-for-test (DFT) features
- Patent number 8,848,429
- Issue date Sep 30, 2014
- QUALCOMM Incorporated
- Ramaprasath Vilangudipitchai
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION
- Publication number 20200168604
- Publication date May 28, 2020
- QUALCOMM Incorporated
- Seid Hadi RASOULI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION
- Publication number 20200152630
- Publication date May 14, 2020
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION
- Publication number 20180342515
- Publication date Nov 29, 2018
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
STANDARD CELL ARCHITECTURE WITH M1 LAYER UNIDIRECTIONAL ROUTING
- Publication number 20180122824
- Publication date May 3, 2018
- QUALCOMM Incorporated
- Mukul GUPTA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION
- Publication number 20170221826
- Publication date Aug 3, 2017
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HYBRID COLORING METHODOLOGY FOR MULTI-PATTERN TECHNOLOGY
- Publication number 20160370699
- Publication date Dec 22, 2016
- QUALCOMM Incorporated
- Xiangdong CHEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CROSS-COUPLE IN MULTI-HEIGHT SEQUENTIAL CELLS FOR UNI-DIRECTIONAL M1
- Publication number 20160351490
- Publication date Dec 1, 2016
- QUALCOMM Incorporated
- Mukul GUPTA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE FOR COUPLING METAL LAYER INTERCONNECTS IN A SEMICONDUCTOR...
- Publication number 20160343661
- Publication date Nov 24, 2016
- QUALCOMM Incorporated
- Mukul GUPTA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VOLTAGE COMPARATOR
- Publication number 20160248414
- Publication date Aug 25, 2016
- QUALCOMM Incorporated
- Ramaprasath Vilangudipitchai
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
STANDARD CELL ARCHITECTURE WITH M1 LAYER UNIDIRECTIONAL ROUTING
- Publication number 20150333008
- Publication date Nov 19, 2015
- QUALCOMM Incorporated
- Mukul GUPTA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VARIABLE INTERCONNECT PITCH FOR IMPROVED PERFORMANCE
- Publication number 20150301973
- Publication date Oct 22, 2015
- QUALCOMM Incorporated
- Kern RIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MASK ASSIGNMENT TECHNIQUE FOR M1 METAL LAYER IN TRIPLE-PATTERNING L...
- Publication number 20150302129
- Publication date Oct 22, 2015
- QUALCOMM Incorporated
- Xiangdong CHEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DOUBLE PATTERNED STACKING TECHNIQUE
- Publication number 20150287709
- Publication date Oct 8, 2015
- QUALCOMM Incorporated
- HariKrishna CHINTARLAPALLI REDDY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH PERFORMANCE STANDARD CELL
- Publication number 20150249076
- Publication date Sep 3, 2015
- QUALCOMM Incorporated
- XIANGDONG CHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GROUNDING DUMMY GATE IN SCALED LAYOUT DESIGN
- Publication number 20150235948
- Publication date Aug 20, 2015
- QUALCOMM Incorporated
- Stanley Seungchul SONG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIGITAL CIRCUIT DESIGN WITH SEMI-CONTINUOUS DIFFUSION STANDARD CELL
- Publication number 20150221639
- Publication date Aug 6, 2015
- QUALCOMM Incorporated
- Xiangdong CHEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE LAYOUT ARCHITECTURE FOR METAL-PROGRAMMABLE VOLTAGE LEVEL S...
- Publication number 20150109045
- Publication date Apr 23, 2015
- QUALCOMM Incorporated
- Ramaprasath Vilangudipitchai
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LATCH-BASED ARRAY WITH ENHANCED READ ENABLE FAULT TESTING
- Publication number 20150070973
- Publication date Mar 12, 2015
- QUALCOMM Incorporated
- Gaurav Bhargava
- G11 - INFORMATION STORAGE
Information Patent Application
LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION
- Publication number 20150054567
- Publication date Feb 26, 2015
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION
- Publication number 20150054568
- Publication date Feb 26, 2015
- QUALCOMM Incorporated
- Seid Hadi RASOULI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOC DESIGN WITH CRITICAL TECHNOLOGY PITCH ALIGNMENT
- Publication number 20150028495
- Publication date Jan 29, 2015
- QUALCOMM Incorporated
- Xiangdong CHEN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Latch-based Array with Robust Design-for-Test (DFT) Features
- Publication number 20140226395
- Publication date Aug 14, 2014
- QUALCOMM Incorporated
- Ramaprasath Vilangudipitchai
- G11 - INFORMATION STORAGE
Information Patent Application
CLOCK-GATED SYNCHRONIZER
- Publication number 20140225655
- Publication date Aug 14, 2014
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
HIGH FREQUENCY SYNCHRONIZER
- Publication number 20140211893
- Publication date Jul 31, 2014
- QUALCOMM Incorporated
- Seid Hadi Rasouli
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Ohsang Kwon

Person

Patents Grantslast 30 patents

Layout construction for addressing electromigration

Layout construction for addressing electromigration

Layout construction for addressing electromigration

Standard cell architecture with M1 layer unidirectional routing

Layout construction for addressing electromigration

Hybrid coloring methodology for multi-pattern technology

Layout construction for addressing electromigration

Layout construction for addressing electromigration

Standard cell architecture with M1 layer unidirectional routing

Layout construction for addressing electromigration

Voltage comparator

Layout construction for addressing electromigration

Cross-couple in multi-height sequential cells for uni-directional M1

Grounding dummy gate in scaled layout design

SOC design with critical technology pitch alignment

High performance standard cell with continuous oxide definition and...

Continuous diffusion configurable standard cell architecture

Digital circuit design with semi-continuous diffusion standard cell

High frequency synchronizer

Latch-based array with enhanced read enable fault testing

Latch-based array with robust design-for-test (DFT) features

Patents Applicationslast 30 patents

LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION

LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION

LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION

STANDARD CELL ARCHITECTURE WITH M1 LAYER UNIDIRECTIONAL ROUTING

LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION

HYBRID COLORING METHODOLOGY FOR MULTI-PATTERN TECHNOLOGY

CROSS-COUPLE IN MULTI-HEIGHT SEQUENTIAL CELLS FOR UNI-DIRECTIONAL M1

STRUCTURE FOR COUPLING METAL LAYER INTERCONNECTS IN A SEMICONDUCTOR...

VOLTAGE COMPARATOR

STANDARD CELL ARCHITECTURE WITH M1 LAYER UNIDIRECTIONAL ROUTING

VARIABLE INTERCONNECT PITCH FOR IMPROVED PERFORMANCE

MASK ASSIGNMENT TECHNIQUE FOR M1 METAL LAYER IN TRIPLE-PATTERNING L...

DOUBLE PATTERNED STACKING TECHNIQUE

HIGH PERFORMANCE STANDARD CELL

GROUNDING DUMMY GATE IN SCALED LAYOUT DESIGN

DIGITAL CIRCUIT DESIGN WITH SEMI-CONTINUOUS DIFFUSION STANDARD CELL

SCALABLE LAYOUT ARCHITECTURE FOR METAL-PROGRAMMABLE VOLTAGE LEVEL S...

LATCH-BASED ARRAY WITH ENHANCED READ ENABLE FAULT TESTING

LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION

LAYOUT CONSTRUCTION FOR ADDRESSING ELECTROMIGRATION

SOC DESIGN WITH CRITICAL TECHNOLOGY PITCH ALIGNMENT

Latch-based Array with Robust Design-for-Test (DFT) Features

CLOCK-GATED SYNCHRONIZER

HIGH FREQUENCY SYNCHRONIZER