Patrick Edward Perry

Person

Essex Junction, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory test with in-line error correction code logic to test memory...
- Patent number 9,734,920
- Issue date Aug 15, 2017
- International Business Machines Corporation
- Kevin W. Gorman
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory test with in-line error correction code logic
- Patent number 9,224,503
- Issue date Dec 29, 2015
- International Business Machines Corporation
- Kevin W. Gorman
- G11 - INFORMATION STORAGE
Information Patent Grant
In-line code suppression
- Patent number 6,880,074
- Issue date Apr 12, 2005
- International Business Machines Corporation
- Patrick E. Perry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-power critical error rate communications controller
- Patent number 6,802,033
- Issue date Oct 5, 2004
- International Business Machines Corporation
- Claude L. Bertin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for reducing power consumption in VLSI circuit...
- Patent number 6,711,719
- Issue date Mar 23, 2004
- International Business Machines Corporation
- John Maxwell Cohn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Real time function view system and method
- Patent number 6,678,847
- Issue date Jan 13, 2004
- International Business Machines Corporation
- Patrick E. Perry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stacked voltage rails for low-voltage DC distribution
- Patent number 6,479,974
- Issue date Nov 12, 2002
- International Business Machines Corporation
- John Maxwell Cohn
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Managing VT for reduced power using power setting commands in the i...
- Patent number 6,477,654
- Issue date Nov 5, 2002
- International Business Machines Corporation
- Alvar Antonio Dean
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Control of multiple equivalent functional units for power reduction
- Patent number 6,317,840
- Issue date Nov 13, 2001
- International Business Machines Corporation
- Alvar A. Dean
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Split I/O circuit for performance optimization of digital circuits
- Patent number 6,269,468
- Issue date Jul 31, 2001
- International Business Machines Corporation
- Alvar Dean
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device and method to reduce power consumption in integrated semicon...
- Patent number 6,097,243
- Issue date Aug 1, 2000
- International Business Machines Corporation
- Claude L. Bertin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Redundant vias
- Patent number 6,026,224
- Issue date Feb 15, 2000
- International Business Machines Corporation
- Laura Rohwedder Darden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low powering apparatus for automatic reduction of power in active a...
- Patent number 6,011,383
- Issue date Jan 4, 2000
- International Business Machines Corporation
- Alvar A. Dean
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
True/complement output bus for reduced simulataneous switching noise
- Patent number 5,874,833
- Issue date Feb 23, 1999
- International Business Machines Corporation
- Patrick Edward Perry
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Output driver that parks output before going tristate
- Patent number 5,784,575
- Issue date Jul 21, 1998
- International Business Machines Corporation
- Steven F. Oakland
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wiring layout design method and system for integrated circuits
- Patent number 5,341,310
- Issue date Aug 23, 1994
- International Business Machines Corporation
- Scott W. Gould
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Current limiting clamp circuit
- Patent number 5,182,468
- Issue date Jan 26, 1993
- IBM Corporation
- Charles K. Erdelyi
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
MEMORY TEST WITH IN-LINE ERROR CORRECTION CODE LOGIC
- Publication number 20160019981
- Publication date Jan 21, 2016
- International Business Machines Corporation
- Kevin W. GORMAN
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY TEST WITH IN-LINE ERROR CORRECTION CODE LOGIC
- Publication number 20140143619
- Publication date May 22, 2014
- International Business Machines Corporation
- Kevin W. GORMAN
- G11 - INFORMATION STORAGE
Information Patent Application
DESIGN STRUCTURE FOR ADAPTIVE ROUTE PLANNING FOR GPS-BASED NAVIGATION
- Publication number 20080215237
- Publication date Sep 4, 2008
- International Business Machines Corporation
- Patrick E. Perry
- G01 - MEASURING TESTING
Information Patent Application
ADAPTIVE ROUTE PLANNING FOR GPS-BASED NAVIGATION
- Publication number 20070271034
- Publication date Nov 22, 2007
- Patrick E. Perry
- G01 - MEASURING TESTING
Information Patent Application
Method and apparatus for reducing power consumption in VLSI circuit...
- Publication number 20030033580
- Publication date Feb 13, 2003
- International Business Machines Corporation
- John Maxwell Cohn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
In-line code suppression
- Publication number 20020103992
- Publication date Aug 1, 2002
- Patrick E. Perry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Stacked voltage rails for low-voltage DC distribution
- Publication number 20020084824
- Publication date Jul 4, 2002
- International Business Machines Corporation
- John Maxwell Cohn
- H01 - BASIC ELECTRIC ELEMENTS

Patrick Edward Perry

Person

Patents Grantslast 30 patents

Memory test with in-line error correction code logic to test memory...

Memory test with in-line error correction code logic

In-line code suppression

Low-power critical error rate communications controller

Method and apparatus for reducing power consumption in VLSI circuit...

Real time function view system and method

Stacked voltage rails for low-voltage DC distribution

Managing VT for reduced power using power setting commands in the i...

Control of multiple equivalent functional units for power reduction

Split I/O circuit for performance optimization of digital circuits

Device and method to reduce power consumption in integrated semicon...

Redundant vias

Low powering apparatus for automatic reduction of power in active a...

True/complement output bus for reduced simulataneous switching noise

Output driver that parks output before going tristate

Wiring layout design method and system for integrated circuits

Current limiting clamp circuit

Patents Applicationslast 30 patents

MEMORY TEST WITH IN-LINE ERROR CORRECTION CODE LOGIC

MEMORY TEST WITH IN-LINE ERROR CORRECTION CODE LOGIC

DESIGN STRUCTURE FOR ADAPTIVE ROUTE PLANNING FOR GPS-BASED NAVIGATION

ADAPTIVE ROUTE PLANNING FOR GPS-BASED NAVIGATION

Method and apparatus for reducing power consumption in VLSI circuit...

In-line code suppression

Stacked voltage rails for low-voltage DC distribution