Patrick Heyne

Person

Muchen, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Delay circuit
- Patent number 7,629,820
- Issue date Dec 8, 2009
- Qimonda AG
- Patrick Heyne
- G11 - INFORMATION STORAGE
Information Patent Grant
Delay locked loop
- Patent number 7,457,392
- Issue date Nov 25, 2008
- Infineon Technologies AG
- Christian Weis
- G11 - INFORMATION STORAGE
Information Patent Grant
Device and method for the synchronization of clock signals and adju...
- Patent number 7,414,445
- Issue date Aug 19, 2008
- Qimonda AG
- Patrick Heyne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read latency control circuit
- Patent number 7,404,018
- Issue date Jul 22, 2008
- Infineon Technologies AG
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Delay locked loop and method for setting a delay chain
- Patent number 7,391,245
- Issue date Jun 24, 2008
- Infineon Technologies AG
- Patrick Heyne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and circuit arrangement for resetting an integrated circuit
- Patent number 7,363,561
- Issue date Apr 22, 2008
- Infineon Technologies AG
- Stefan Dietrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device to be used in the synchronization of clock pulses, as well a...
- Patent number 7,304,515
- Issue date Dec 4, 2007
- Infineon Technologies AG
- Martin Brox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integratable, controllable delay device, use of a delay device, as...
- Patent number 7,126,401
- Issue date Oct 24, 2006
- Infineon Technologies AG
- Patrick Heyne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Delay locked loop
- Patent number 7,016,452
- Issue date Mar 21, 2006
- Infineon Technologies AG
- Torsten Partsch
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated synchronous memory and memory configuration having a mem...
- Patent number 6,967,893
- Issue date Nov 22, 2005
- Infineon Tecnologies AG
- Patrick Heyne
- G11 - INFORMATION STORAGE
Information Patent Grant
Synchronous integrated memory
- Patent number 6,928,025
- Issue date Aug 9, 2005
- Infineon Technologies AG
- Thomas Hein
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and logic/memory module for correcting the duty cycle of at...
- Patent number 6,806,752
- Issue date Oct 19, 2004
- Infineon Technologies AG
- Patrick Heyne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit configuration for generating a controllable output voltage
- Patent number 6,784,650
- Issue date Aug 31, 2004
- Infienon Technologies AG
- Thomas Hein
- G05 - CONTROLLING REGULATING
Information Patent Grant
Optimized-delay multiplexer
- Patent number 6,756,820
- Issue date Jun 29, 2004
- Siemens Aktiengesellschaft
- Patrick Heyne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrable, controllable delay device, delay device in a control lo...
- Patent number 6,737,901
- Issue date May 18, 2004
- Infineon Technologies AG
- Thomas Hein
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit having a test operating mode and method for test...
- Patent number 6,670,802
- Issue date Dec 30, 2003
- Infineon Technologies AG
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Delay locked loop for generating complementary clock signals
- Patent number 6,661,265
- Issue date Dec 9, 2003
- Infineon Technologies AG
- Torsten Partsch
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Current mirror circuit
- Patent number 6,657,422
- Issue date Dec 2, 2003
- Infineon Technologies AG
- Patrick Heyne
- G05 - CONTROLLING REGULATING
Information Patent Grant
Semiconductor memory having a delay locked loop
- Patent number 6,584,021
- Issue date Jun 24, 2003
- Infineon Technologies AG
- Patrick Heyne
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit configuration for enabling a clock signal in a manner depen...
- Patent number 6,573,754
- Issue date Jun 3, 2003
- Infineon Technologies AG
- Ullrich Menczigar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Voltage pump with switch-on control
- Patent number 6,542,389
- Issue date Apr 1, 2003
- Infineon Technology AG
- Stefan Dietrich
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Integrated memory having a row access controller for activating and...
- Patent number 6,532,188
- Issue date Mar 11, 2003
- Infineon Technologies AG
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Grant
Configuration for testing a plurality of memory chips on a wafer
- Patent number 6,529,028
- Issue date Mar 4, 2003
- Infineon Technologies AG
- Dieter Härle
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit configuration for programming a delay in a signal path
- Patent number 6,480,024
- Issue date Nov 12, 2002
- Infineon Technologies AG
- Stefan Dietrich
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Delivering a fine delay stage for a delay locked loop
- Patent number 6,472,921
- Issue date Oct 29, 2002
- Siemens Aktiengesellschaft
- Rajashekhar Rao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit configuration for compensating runtime and pulse-duty-facto...
- Patent number 6,469,563
- Issue date Oct 22, 2002
- Infineon Technologies AG
- Patrick Heyne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Memory component with short access time
- Patent number 6,388,944
- Issue date May 14, 2002
- Infineon Technologies AG
- Peter Schrögmeier
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit configuration for generating an output clock signal with op...
- Patent number 6,366,527
- Issue date Apr 2, 2002
- Infineon Technologies AG
- Thomas Hein
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit with a phase locked loop
- Patent number 6,351,167
- Issue date Feb 26, 2002
- Siemens Aktiengesellschaft
- Thomas Hein
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit for producing two output clock signals at levels...
- Patent number 6,307,416
- Issue date Oct 23, 2001
- Infineon Technologies AG
- Patrick Heyne
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Delay Circuit
- Publication number 20080074159
- Publication date Mar 27, 2008
- QIMONDA AG
- Patrick Heyne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Amplifier Circuit and Method for Correcting the Duty Ratio of a Dif...
- Publication number 20070285139
- Publication date Dec 13, 2007
- QIMONDA AG
- Patrick Heyne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Signal delay loop and method for locking a signal delay loop
- Publication number 20070273416
- Publication date Nov 29, 2007
- Patrick Heyne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Device and method for the synchronization of clock signals and adju...
- Publication number 20070182470
- Publication date Aug 9, 2007
- Patrick Heyne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Delay locked loop and method for setting a delay chain
- Publication number 20060273834
- Publication date Dec 7, 2006
- Patrick Heyne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Circuit arrangement for generating a synchronization signal
- Publication number 20060214709
- Publication date Sep 28, 2006
- Aaron Nygren
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Read latency control circuit
- Publication number 20050270852
- Publication date Dec 8, 2005
- Infineon Technologies AG
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Application
Method and circuit arrangement for resetting an integrated circuit
- Publication number 20050253638
- Publication date Nov 17, 2005
- Infineon Technologies AG
- Stefan Dietrich
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integratable, controllable delay device, use of a delay device, as...
- Publication number 20050218954
- Publication date Oct 6, 2005
- Patrick Heyne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Device to be used in the synchronization of clock pulses, as well a...
- Publication number 20050179478
- Publication date Aug 18, 2005
- Infineon Technologies AG
- Martin Brox
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated synchronous memory and memory configuration having a mem...
- Publication number 20040022106
- Publication date Feb 5, 2004
- Patrick Heyne
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit configuration for generating a controllable output voltage
- Publication number 20030205992
- Publication date Nov 6, 2003
- Thomas Hein
- G05 - CONTROLLING REGULATING
Information Patent Application
Method and logic/memory module for correcting the duty cycle of at...
- Publication number 20030128061
- Publication date Jul 10, 2003
- Patrick Heyne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Delay locked loop
- Publication number 20030094984
- Publication date May 22, 2003
- Christian Weis
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Integrable, controllable delay device, delay device in a control lo...
- Publication number 20030085747
- Publication date May 8, 2003
- Thomas Hein
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Delay locked loop
- Publication number 20030012322
- Publication date Jan 16, 2003
- Torsten Partsch
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Delay locked loop for generating complementary clock signals
- Publication number 20030001636
- Publication date Jan 2, 2003
- Torsten Partsch
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Circuit configuration for enabling a clock signal in a manner depen...
- Publication number 20020153924
- Publication date Oct 24, 2002
- Ullrich Menczigar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Integrated memory having a row access controller for activating and...
- Publication number 20020141279
- Publication date Oct 3, 2002
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated circuit having a test operating mode and method for test...
- Publication number 20020133750
- Publication date Sep 19, 2002
- Stefan Dietrich
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor memory having a delay locked loop
- Publication number 20020093855
- Publication date Jul 18, 2002
- Patrick Heyne
- G11 - INFORMATION STORAGE
Information Patent Application
Current mirror circuit
- Publication number 20020089319
- Publication date Jul 11, 2002
- Patrick Heyne
- G05 - CONTROLLING REGULATING
Information Patent Application
Circuit configuration for programming a delay in a signal path
- Publication number 20020079925
- Publication date Jun 27, 2002
- Stefan Dietrich
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Voltage pump with switch-on control
- Publication number 20020075707
- Publication date Jun 20, 2002
- Stefan Dietrich
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
Circuit configuration for compensating runtime and pulse-duty-facto...
- Publication number 20020021155
- Publication date Feb 21, 2002
- Patrick Heyne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Memory component with short access time
- Publication number 20010038566
- Publication date Nov 8, 2001
- Peter Schrogmeier
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit configuration for generating an output clock signal with op...
- Publication number 20010033523
- Publication date Oct 25, 2001
- Thomas Hein
- G11 - INFORMATION STORAGE

Patrick Heyne

Person

Patents Grantslast 30 patents

Delay circuit

Delay locked loop

Device and method for the synchronization of clock signals and adju...

Read latency control circuit

Delay locked loop and method for setting a delay chain

Method and circuit arrangement for resetting an integrated circuit

Device to be used in the synchronization of clock pulses, as well a...

Integratable, controllable delay device, use of a delay device, as...

Delay locked loop

Integrated synchronous memory and memory configuration having a mem...

Synchronous integrated memory

Method and logic/memory module for correcting the duty cycle of at...

Circuit configuration for generating a controllable output voltage

Optimized-delay multiplexer

Integrable, controllable delay device, delay device in a control lo...

Integrated circuit having a test operating mode and method for test...

Delay locked loop for generating complementary clock signals

Current mirror circuit

Semiconductor memory having a delay locked loop

Circuit configuration for enabling a clock signal in a manner depen...

Voltage pump with switch-on control

Integrated memory having a row access controller for activating and...

Configuration for testing a plurality of memory chips on a wafer

Circuit configuration for programming a delay in a signal path

Delivering a fine delay stage for a delay locked loop

Circuit configuration for compensating runtime and pulse-duty-facto...

Memory component with short access time

Circuit configuration for generating an output clock signal with op...

Integrated circuit with a phase locked loop

Integrated circuit for producing two output clock signals at levels...

Patents Applicationslast 30 patents

Delay Circuit

Amplifier Circuit and Method for Correcting the Duty Ratio of a Dif...

Signal delay loop and method for locking a signal delay loop

Device and method for the synchronization of clock signals and adju...

Delay locked loop and method for setting a delay chain

Circuit arrangement for generating a synchronization signal

Read latency control circuit

Method and circuit arrangement for resetting an integrated circuit

Integratable, controllable delay device, use of a delay device, as...

Device to be used in the synchronization of clock pulses, as well a...

Integrated synchronous memory and memory configuration having a mem...

Circuit configuration for generating a controllable output voltage

Method and logic/memory module for correcting the duty cycle of at...

Delay locked loop

Integrable, controllable delay device, delay device in a control lo...

Delay locked loop

Delay locked loop for generating complementary clock signals

Circuit configuration for enabling a clock signal in a manner depen...

Integrated memory having a row access controller for activating and...

Integrated circuit having a test operating mode and method for test...

Semiconductor memory having a delay locked loop

Current mirror circuit

Circuit configuration for programming a delay in a signal path

Voltage pump with switch-on control

Circuit configuration for compensating runtime and pulse-duty-facto...

Memory component with short access time

Circuit configuration for generating an output clock signal with op...