Patrick Morrow

Person

Portland, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Gate-to-gate isolation for stacked transistor architecture via sele...
- Patent number 12,369,399
- Issue date Jul 22, 2025
- Intel Corporation
- Willy Rachmady
Information Patent Grant
Asymmetric gate structures and contacts for stacked transistors
- Patent number 12,342,614
- Issue date Jun 24, 2025
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertical integration scheme and circuit elements architecture for a...
- Patent number 12,310,044
- Issue date May 20, 2025
- Intel Corporation
- Rishabh Mehandru
Information Patent Grant
Backside contact structures and fabrication for metal on both sides...
- Patent number 12,288,810
- Issue date Apr 29, 2025
- Intel Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sideways vias in isolation areas to contact interior layers in stac...
- Patent number 12,255,137
- Issue date Mar 18, 2025
- Intel Corporation
- Ehren Mannebach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming an oxide volume within a fin
- Patent number 12,224,202
- Issue date Feb 11, 2025
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate-all-around integrated circuit structures having removed substrate
- Patent number 12,199,143
- Issue date Jan 14, 2025
- Intel Corporation
- Biswajeet Guha
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic assemblies
- Patent number 12,176,323
- Issue date Dec 24, 2024
- Intel Corporation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked source-drain-gate connection and process for forming such
- Patent number 12,148,806
- Issue date Nov 19, 2024
- Intel Corporation
- Ehren Mannebach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interconnect techniques for electrically connecting source/drain re...
- Patent number 12,107,085
- Issue date Oct 1, 2024
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wrap-around source/drain method of making contacts for backside metals
- Patent number 12,100,761
- Issue date Sep 24, 2024
- Intel Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wrap-around source/drain method of making contacts for backside metals
- Patent number 12,100,762
- Issue date Sep 24, 2024
- Intel Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertically stacked finFETs and shared gate patterning
- Patent number 12,100,623
- Issue date Sep 24, 2024
- Intel Corporation
- Aaron Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Backside contacts for semiconductor devices
- Patent number 12,080,605
- Issue date Sep 3, 2024
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked transistors
- Patent number 12,057,494
- Issue date Aug 6, 2024
- Intel Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
PN-body-tied field effect transistors
- Patent number 12,051,723
- Issue date Jul 30, 2024
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Epitaxial layer with substantially parallel sides
- Patent number 12,020,929
- Issue date Jun 25, 2024
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit device with crenellated metal trace layout
- Patent number 11,996,362
- Issue date May 28, 2024
- Intel Corporation
- Patrick Morrow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stacked forksheet transistors
- Patent number 11,996,411
- Issue date May 28, 2024
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-level spin logic
- Patent number 11,990,899
- Issue date May 21, 2024
- Intel Corporation
- Sasikanth Manipatruni
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus with multi-wafer based device and method for forming such
- Patent number 11,948,831
- Issue date Apr 2, 2024
- Intel Corporation
- Anup Pancholi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Vertically spaced intra-level interconnect line metallization for i...
- Patent number 11,948,874
- Issue date Apr 2, 2024
- Intel Corporation
- Kevin L. Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sideways vias in isolation areas to contact interior layers in stac...
- Patent number 11,942,416
- Issue date Mar 26, 2024
- Intel Corporation
- Ehren Mannebach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit contact structures
- Patent number 11,942,526
- Issue date Mar 26, 2024
- Intel Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-silicon N-type and P-type stacked transistors for integrated ci...
- Patent number 11,935,891
- Issue date Mar 19, 2024
- Intel Corporation
- Gilbert Dewey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Backside contact structures and fabrication for metal on both sides...
- Patent number 11,935,933
- Issue date Mar 19, 2024
- Intel Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked source-drain-gate connection and process for forming such
- Patent number 11,916,118
- Issue date Feb 27, 2024
- Intel Corporation
- Ehren Mannebach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacked trigate transistors with dielectric isolation and process f...
- Patent number 11,894,372
- Issue date Feb 6, 2024
- Intel Corporation
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Back side processing of integrated circuit structures to form insul...
- Patent number 11,894,262
- Issue date Feb 6, 2024
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metallization structures for stacked device connectivity and their...
- Patent number 11,869,894
- Issue date Jan 9, 2024
- Intel Corporation
- Aaron D. Lilak
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT STRUCTURES WITH SUB-FIN ISOLATION
- Publication number 20250227993
- Publication date Jul 10, 2025
- Intel Corporation
- Willy RACHMADY
Information Patent Application
BACKSIDE CONTACT STRUCTURES AND FABRICATION FOR METAL ON BOTH SIDES...
- Publication number 20250220952
- Publication date Jul 3, 2025
- Intel Corporation
- Patrick MORROW
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING REMOVED SUBSTRATE
- Publication number 20250107181
- Publication date Mar 27, 2025
- Intel Corporation
- Biswajeet GUHA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES HAVING STACKED TRANSISTORS WITH BACKS...
- Publication number 20250107061
- Publication date Mar 27, 2025
- Intel Corporation
- Patrick MORROW
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC ASSEMBLIES
- Publication number 20250070083
- Publication date Feb 27, 2025
- Intel Corporation
- Adel A. ELSHERBINI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR WITH CHANNEL-SYMMETRIC GATE
- Publication number 20250006810
- Publication date Jan 2, 2025
- Intel Corporation
- Shao-Ming Koh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WRAP-AROUND SOURCE/DRAIN METHOD OF MAKING CONTACTS FOR BACKSIDE METALS
- Publication number 20240413237
- Publication date Dec 12, 2024
- Intel Corporation
- Patrick MORROW
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE WITH BACKSIDE CONTACT STITCHING
- Publication number 20240405085
- Publication date Dec 5, 2024
- Intel Corporation
- Ehren MANNEBACH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACKSIDE CONTACTS FOR SEMICONDUCTOR DEVICES
- Publication number 20240371700
- Publication date Nov 7, 2024
- Intel Corporation
- Aaron D. LILAK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
N-P BALANCED MULTI-PORT REGISTER FILE WITH COMPLEMENTARY FIELD-EFFE...
- Publication number 20240331761
- Publication date Oct 3, 2024
- Intel Corporation
- Charles Augustine
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES WITH SUB-FIN ISOLATION
- Publication number 20240332301
- Publication date Oct 3, 2024
- Intel Corporation
- Willy RACHMADY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TRANSISTOR WITH CHANNEL-SYMMETRIC GATE
- Publication number 20240332290
- Publication date Oct 3, 2024
- Intel Corporation
- Shao-Ming Koh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED TRANSISTORS
- Publication number 20240332403
- Publication date Oct 3, 2024
- Intel Corporation
- Patrick MORROW
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICALLY SPACED INTRA-LEVEL INTERCONNECT LINE METALLIZATION FOR I...
- Publication number 20240243052
- Publication date Jul 18, 2024
- Intel Corporation
- Kevin L. Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED FORKSHEET TRANSISTORS
- Publication number 20240234422
- Publication date Jul 11, 2024
- Intel Corporation
- Cheng-Ying HUANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED BACKBONE FOR FORKSHEET TRANSISTORS
- Publication number 20240213250
- Publication date Jun 27, 2024
- Intel Corporation
- Shao Ming KOH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High Density Transistor and Routing Track Architecture
- Publication number 20240202415
- Publication date Jun 20, 2024
- Intel Corporation
- Quan Shi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DEVICE STRUCTURES AND DOUBLE-SIDED ELECTRICAL TE...
- Publication number 20240194533
- Publication date Jun 13, 2024
- Intel Corporation
- Valluri R. RAO
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT STRUCTURES WITH CAVITY SPACERS
- Publication number 20240186398
- Publication date Jun 6, 2024
- Intel Corporation
- Aaron D. LILAK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACKSIDE CONTACTED SUB-FIN DIODES
- Publication number 20240170581
- Publication date May 23, 2024
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-TRANSISTOR EMBEDDED DYNAMIC RANDOM ACCESS MEMORY GAIN CELL IN...
- Publication number 20240161817
- Publication date May 16, 2024
- Charles Augustine
- G11 - INFORMATION STORAGE
Information Patent Application
SIDEWAYS VIAS IN ISOLATION AREAS TO CONTACT INTERIOR LAYERS IN STAC...
- Publication number 20240162141
- Publication date May 16, 2024
- Intel Corporation
- Ehren MANNEBACH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACKSIDE CONTACT STRUCTURES AND FABRICATION FOR METAL ON BOTH SIDES...
- Publication number 20240154011
- Publication date May 9, 2024
- Intel Corporation
- Patrick MORROW
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED SOURCE-DRAIN-GATE CONNECTION AND PROCESS FOR FORMING SUCH
- Publication number 20240145557
- Publication date May 2, 2024
- Intel Corporation
- Ehren MANNEBACH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT CONTACT STRUCTURES
- Publication number 20240128340
- Publication date Apr 18, 2024
- Intel Corporation
- Patrick Morrow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT (IC) DEVICE WITH METAL LAYER INCLUDING STAGGERED...
- Publication number 20240105589
- Publication date Mar 28, 2024
- Intel Corporation
- Shao Ming Koh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE ARCHITECTURE FOR QUASI-MONOLITHIC CHIP WITH BACKSIDE POWER
- Publication number 20240063120
- Publication date Feb 22, 2024
- Intel Corporation
- Adel A. Elsherbini
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-PORTED REGISTER FILE WITH CFETS
- Publication number 20240053987
- Publication date Feb 15, 2024
- Intel Corporation
- Charles Augustine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CH...
- Publication number 20240047559
- Publication date Feb 8, 2024
- Intel Corporation
- Willy RACHMADY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOWER DEVICE ACCESS IN STACKED TRANSISTOR DEVICES
- Publication number 20230420460
- Publication date Dec 28, 2023
- Intel Corporation
- Cheng-Ying Huang
- H01 - BASIC ELECTRIC ELEMENTS

Patrick Morrow

Person

Patents Grantslast 30 patents

Gate-to-gate isolation for stacked transistor architecture via sele...

Asymmetric gate structures and contacts for stacked transistors

Vertical integration scheme and circuit elements architecture for a...

Backside contact structures and fabrication for metal on both sides...

Sideways vias in isolation areas to contact interior layers in stac...

Forming an oxide volume within a fin

Gate-all-around integrated circuit structures having removed substrate

Microelectronic assemblies

Stacked source-drain-gate connection and process for forming such

Interconnect techniques for electrically connecting source/drain re...

Wrap-around source/drain method of making contacts for backside metals

Wrap-around source/drain method of making contacts for backside metals

Vertically stacked finFETs and shared gate patterning

Backside contacts for semiconductor devices

Stacked transistors

PN-body-tied field effect transistors

Epitaxial layer with substantially parallel sides

Integrated circuit device with crenellated metal trace layout

Stacked forksheet transistors

Multi-level spin logic

Apparatus with multi-wafer based device and method for forming such

Vertically spaced intra-level interconnect line metallization for i...

Sideways vias in isolation areas to contact interior layers in stac...

Integrated circuit contact structures

Non-silicon N-type and P-type stacked transistors for integrated ci...

Backside contact structures and fabrication for metal on both sides...

Stacked source-drain-gate connection and process for forming such

Stacked trigate transistors with dielectric isolation and process f...

Back side processing of integrated circuit structures to form insul...

Metallization structures for stacked device connectivity and their...

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT STRUCTURES WITH SUB-FIN ISOLATION

BACKSIDE CONTACT STRUCTURES AND FABRICATION FOR METAL ON BOTH SIDES...

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING REMOVED SUBSTRATE

INTEGRATED CIRCUIT STRUCTURES HAVING STACKED TRANSISTORS WITH BACKS...

MICROELECTRONIC ASSEMBLIES

TRANSISTOR WITH CHANNEL-SYMMETRIC GATE

WRAP-AROUND SOURCE/DRAIN METHOD OF MAKING CONTACTS FOR BACKSIDE METALS

INTEGRATED CIRCUIT STRUCTURE WITH BACKSIDE CONTACT STITCHING

BACKSIDE CONTACTS FOR SEMICONDUCTOR DEVICES

N-P BALANCED MULTI-PORT REGISTER FILE WITH COMPLEMENTARY FIELD-EFFE...

INTEGRATED CIRCUIT STRUCTURES WITH SUB-FIN ISOLATION

TRANSISTOR WITH CHANNEL-SYMMETRIC GATE

STACKED TRANSISTORS

VERTICALLY SPACED INTRA-LEVEL INTERCONNECT LINE METALLIZATION FOR I...

STACKED FORKSHEET TRANSISTORS

SELF-ALIGNED BACKBONE FOR FORKSHEET TRANSISTORS

High Density Transistor and Routing Track Architecture

INTEGRATED CIRCUIT DEVICE STRUCTURES AND DOUBLE-SIDED ELECTRICAL TE...

INTEGRATED CIRCUIT STRUCTURES WITH CAVITY SPACERS

BACKSIDE CONTACTED SUB-FIN DIODES

THREE-TRANSISTOR EMBEDDED DYNAMIC RANDOM ACCESS MEMORY GAIN CELL IN...

SIDEWAYS VIAS IN ISOLATION AREAS TO CONTACT INTERIOR LAYERS IN STAC...

BACKSIDE CONTACT STRUCTURES AND FABRICATION FOR METAL ON BOTH SIDES...

STACKED SOURCE-DRAIN-GATE CONNECTION AND PROCESS FOR FORMING SUCH

INTEGRATED CIRCUIT CONTACT STRUCTURES

INTEGRATED CIRCUIT (IC) DEVICE WITH METAL LAYER INCLUDING STAGGERED...

PACKAGE ARCHITECTURE FOR QUASI-MONOLITHIC CHIP WITH BACKSIDE POWER

MULTI-PORTED REGISTER FILE WITH CFETS

GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING DEPOPULATED CH...

LOWER DEVICE ACCESS IN STACKED TRANSISTOR DEVICES