Paul A. LaBerge

Person

Shoreview, MN, US

People

Patents Grantslast 30 patents

Information Patent Grant
Switched interface stacked-die memory architecture
- Patent number 10,297,340
- Issue date May 21, 2019
- Micron Technology, Inc.
- Joe M. Jeddeloh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Switched interface stacked-die memory architecture
- Patent number 10,037,818
- Issue date Jul 31, 2018
- Micron Technology, Inc.
- Joe M. Jeddeloh
- G11 - INFORMATION STORAGE
Information Patent Grant
Switched interface stacked-die memory architecture
- Patent number 9,875,814
- Issue date Jan 23, 2018
- Micron Technology, Inc.
- Joe M. Jeddeloh
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-serial interface stacked-die memory architecture
- Patent number 9,524,254
- Issue date Dec 20, 2016
- Micron Technology, Inc.
- Joe M. Jeddeloh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory systems and methods for controlling the timing of receiving...
- Patent number 9,411,538
- Issue date Aug 9, 2016
- Micron Technology, Inc.
- Paul A. LaBerge
- G11 - INFORMATION STORAGE
Information Patent Grant
Switched interface for stacked-die memory architecture with redunda...
- Patent number 9,343,180
- Issue date May 17, 2016
- Micron Technology, Inc.
- Joe M. Jeddeloh
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system and method using stacked memory device dice, and syst...
- Patent number 9,275,698
- Issue date Mar 1, 2016
- Micron Technology, Inc.
- Paul A. LaBerge
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for repairing high capacity/high bandwidth mem...
- Patent number 9,146,811
- Issue date Sep 29, 2015
- Micron Technology, Inc.
- Paul A. LaBerge
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for read synchronization of memory modules
- Patent number 8,880,833
- Issue date Nov 4, 2014
- Micron Technology, Inc.
- Joseph M. Jeddeloh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-serial interface stacked-die memory architecture
- Patent number 8,806,131
- Issue date Aug 12, 2014
- Micron Technology, Inc.
- Joe M. Jeddeloh
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Memory system and method using stacked memory device dice, and syst...
- Patent number 8,793,460
- Issue date Jul 29, 2014
- Micron Technology, Inc.
- Paul A. LaBerge
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked device remapping and repair
- Patent number 8,787,101
- Issue date Jul 22, 2014
- Micron Technology, Inc.
- Brent Keeth
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for repairing high capacity/high bandwidth mem...
- Patent number 8,756,486
- Issue date Jun 17, 2014
- Micron Technology, Inc.
- Paul A. LaBerge
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory systems and methods for controlling the timing of receiving...
- Patent number 8,751,754
- Issue date Jun 10, 2014
- Micron Technology, Inc.
- Paul A. LaBerge
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for controlling timing of output signals
- Patent number 8,705,301
- Issue date Apr 22, 2014
- Micron Technology, Inc.
- Paul A. LaBerge
- G11 - INFORMATION STORAGE
Information Patent Grant
Switched interface stacked-die memory architecture
- Patent number 8,619,481
- Issue date Dec 31, 2013
- Micron Technology, Inc.
- Joe M. Jeddeloh
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system and method using stacked memory device dice, and syst...
- Patent number 8,533,416
- Issue date Sep 10, 2013
- Micron Technology, Inc.
- Paul A. LaBerge
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory systems and methods for controlling the timing of receiving...
- Patent number 8,521,979
- Issue date Aug 27, 2013
- Micron Technology, Inc.
- Paul A. LaBerge
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked device remapping and repair
- Patent number 8,503,258
- Issue date Aug 6, 2013
- Micron Technology, Inc.
- Brent Keeth
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for controlling timing of output signals
- Patent number 8,411,521
- Issue date Apr 2, 2013
- Micron Technology, Inc.
- Paul A. LaBerge
- G11 - INFORMATION STORAGE
Information Patent Grant
Strobe apparatus, systems, and methods
- Patent number 8,406,071
- Issue date Mar 26, 2013
- Micron Technology, Inc.
- James Brian Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for read synchronization of memory modules
- Patent number 8,392,686
- Issue date Mar 5, 2013
- Micron Technology, Inc.
- Joseph M. Jeddeloh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stacked device remapping and repair
- Patent number 8,320,206
- Issue date Nov 27, 2012
- Micron Technology, Inc.
- Brent Keeth
- G11 - INFORMATION STORAGE
Information Patent Grant
Switched interface stacked-die memory architecture
- Patent number 8,254,191
- Issue date Aug 28, 2012
- Micron Technology, Inc.
- Joe M. Jeddeloh
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for an asynchronous data buffer having buffer wri...
- Patent number 8,239,607
- Issue date Aug 7, 2012
- Micron Technology, Inc.
- Paul A. LaBerge
- G11 - INFORMATION STORAGE
Information Patent Grant
Strobe apparatus, systems, and methods
- Patent number 8,169,841
- Issue date May 1, 2012
- Micron Technology, Inc.
- James Brian Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Delay line synchronizer apparatus and method
- Patent number 8,164,375
- Issue date Apr 24, 2012
- Round Rock Research, LLC
- Paul A. LaBerge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Capturing read data
- Patent number 8,065,461
- Issue date Nov 22, 2011
- Micron Technology, Inc.
- Paul A. LaBerge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system and method using stacked memory device dice, and syst...
- Patent number 8,010,866
- Issue date Aug 30, 2011
- Micron Technology, Inc.
- Paul A. LaBerge
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory devices with buffered command address bus
- Patent number 8,006,057
- Issue date Aug 23, 2011
- Round Rock Research, LLC
- Paul A. LaBerge
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
INFORMATION BROADCAST TECHNIQUES FOR STACKED MEMORY ARCHITECTURES
- Publication number 20240403165
- Publication date Dec 5, 2024
- Micron Technology, Inc.
- Nathan A. Eckel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACE TECHNIQUES FOR STACKED MEMORY ARCHITECTURES
- Publication number 20240404581
- Publication date Dec 5, 2024
- Micron Technology, Inc.
- Ameen D. Akel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERFACE LAYOUT FOR STACKED MEMORY ARCHITECTURES
- Publication number 20240402909
- Publication date Dec 5, 2024
- Micron Technology, Inc.
- Nathan A. Eckel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DIE FAULT DETECTION USING A CALIBRATION PIN
- Publication number 20240303157
- Publication date Sep 12, 2024
- Micron Technology, Inc.
- Scott E. Schaefer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIFFERENTIAL STROBE FAULT IDENTIFICATION
- Publication number 20240282400
- Publication date Aug 22, 2024
- Micron Technology, Inc.
- Scott E. Schaefer
- G11 - INFORMATION STORAGE
Information Patent Application
SWITCHED INTERFACE STACKED-DIE MEMORY ARCHITECTURE
- Publication number 20180358111
- Publication date Dec 13, 2018
- Micron Technology, Inc.
- Joe M. Jeddeloh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SWITCHED INTERFACE STACKED-DIE MEMORY ARCHITECTURE
- Publication number 20180114587
- Publication date Apr 26, 2018
- Micron Technology, Inc.
- Joe M. Jeddeloh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SWITCHED INTERFACE STACKED-DIE MEMORY ARCHITECTURE
- Publication number 20160260503
- Publication date Sep 8, 2016
- Micron Technology, Inc.
- Joe M. Jeddeloh
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-SERIAL INTERFACE STACKED-DIE MEMORY ARCHITECTURE
- Publication number 20140351503
- Publication date Nov 27, 2014
- Joe M. Jeddeloh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYST...
- Publication number 20140337570
- Publication date Nov 13, 2014
- Paul A. LaBerge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR REPAIRING HIGH CAPACITY/HIGH BANDWIDTH MEM...
- Publication number 20140298119
- Publication date Oct 2, 2014
- Paul A. LaBerge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEMS AND METHODS FOR CONTROLLING THE TIMING OF RECEIVING...
- Publication number 20140258666
- Publication date Sep 11, 2014
- Micron Technology, Inc.
- Paul A. LaBerge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SWITCHED INTERFACE STACKED-DIE MEMORY ARCHITECTURE
- Publication number 20140112085
- Publication date Apr 24, 2014
- Micron Technology, Inc.
- Joe M. Jeddeloh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYST...
- Publication number 20130346722
- Publication date Dec 26, 2013
- Micron Technology, Inc.
- Paul A. LaBerge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STACKED DEVICE REMAPPING AND REPAIR
- Publication number 20130329510
- Publication date Dec 12, 2013
- Micron Technology, Inc.
- Brent Keeth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEMS AND METHODS FOR CONTROLLING THE TIMING OF RECEIVING...
- Publication number 20130318298
- Publication date Nov 28, 2013
- Micron Technology, Inc.
- Paul A. LaBerge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR CONTROLLING TIMING OF OUTPUT SIGNALS
- Publication number 20130241618
- Publication date Sep 19, 2013
- Micron Technology, Inc.
- Paul A. LaBerge
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND METHOD FOR READ SYNCHRONIZATION OF MEMORY MODULES
- Publication number 20130179658
- Publication date Jul 11, 2013
- Micron Technology, Inc.
- Joseph M. Jeddeloh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STACKED DEVICE REMAPPING AND REPAIR
- Publication number 20130003473
- Publication date Jan 3, 2013
- Micron Technology, Inc.
- Brent Keeth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SWITCHED INTERFACE STACKED-DIE MEMORY ARCHITECTURE
- Publication number 20120320688
- Publication date Dec 20, 2012
- Joe M. Jeddeloh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STROBE APPARATUS, SYSTEMS, AND METHODS
- Publication number 20120213012
- Publication date Aug 23, 2012
- James Brian Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYST...
- Publication number 20110296227
- Publication date Dec 1, 2011
- Micron Technology, Inc.
- PAUL A. LABERGE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-SERIAL INTERFACE STACKED-DIE MEMORY ARCHITECTURE
- Publication number 20110264858
- Publication date Oct 27, 2011
- Joe M. Jeddeloh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR CONTROLLING TIMING OF OUTPUT SIGNALS
- Publication number 20110231143
- Publication date Sep 22, 2011
- Micron Technology, Inc.
- Paul A. LaBerge
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYST...
- Publication number 20110075497
- Publication date Mar 31, 2011
- Micron Technology, Inc.
- PAUL A. LABERGE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR CONTROLLING TIMING OF OUTPUT SIGNALS
- Publication number 20110069561
- Publication date Mar 24, 2011
- Micron Technology, Inc.
- Paul A. LaBerge
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
STACKED DEVICE REMAPPING AND REPAIR
- Publication number 20110060888
- Publication date Mar 10, 2011
- Brent Keeth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CAPTURING READ DATA
- Publication number 20110047312
- Publication date Feb 24, 2011
- Micron Technology, Inc.
- Paul A. LaBerge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STROBE APPARATUS, SYSTEMS, AND METHODS
- Publication number 20100188906
- Publication date Jul 29, 2010
- Micron Technology, Inc.
- James Brian Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICES WITH BUFFERED COMMAND ADDRESS BUS
- Publication number 20100138598
- Publication date Jun 3, 2010
- ROUND ROCK RESEARCH, LLC
- Paul A. LaBerge
- G06 - COMPUTING CALCULATING COUNTING

Paul A. LaBerge

Person

Patents Grantslast 30 patents

Switched interface stacked-die memory architecture

Switched interface stacked-die memory architecture

Switched interface stacked-die memory architecture

Multi-serial interface stacked-die memory architecture

Memory systems and methods for controlling the timing of receiving...

Switched interface for stacked-die memory architecture with redunda...

Memory system and method using stacked memory device dice, and syst...

Method and apparatus for repairing high capacity/high bandwidth mem...

System and method for read synchronization of memory modules

Multi-serial interface stacked-die memory architecture

Memory system and method using stacked memory device dice, and syst...

Stacked device remapping and repair

Method and apparatus for repairing high capacity/high bandwidth mem...

Memory systems and methods for controlling the timing of receiving...

System and method for controlling timing of output signals

Switched interface stacked-die memory architecture

Memory system and method using stacked memory device dice, and syst...

Memory systems and methods for controlling the timing of receiving...

Stacked device remapping and repair

System and method for controlling timing of output signals

Strobe apparatus, systems, and methods

System and method for read synchronization of memory modules

Stacked device remapping and repair

Switched interface stacked-die memory architecture

System and method for an asynchronous data buffer having buffer wri...

Strobe apparatus, systems, and methods

Delay line synchronizer apparatus and method

Capturing read data

Memory system and method using stacked memory device dice, and syst...

Memory devices with buffered command address bus

Patents Applicationslast 30 patents

INFORMATION BROADCAST TECHNIQUES FOR STACKED MEMORY ARCHITECTURES

INTERFACE TECHNIQUES FOR STACKED MEMORY ARCHITECTURES

INTERFACE LAYOUT FOR STACKED MEMORY ARCHITECTURES

MEMORY DIE FAULT DETECTION USING A CALIBRATION PIN

DIFFERENTIAL STROBE FAULT IDENTIFICATION

SWITCHED INTERFACE STACKED-DIE MEMORY ARCHITECTURE

SWITCHED INTERFACE STACKED-DIE MEMORY ARCHITECTURE

SWITCHED INTERFACE STACKED-DIE MEMORY ARCHITECTURE

MULTI-SERIAL INTERFACE STACKED-DIE MEMORY ARCHITECTURE

MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYST...

METHOD AND APPARATUS FOR REPAIRING HIGH CAPACITY/HIGH BANDWIDTH MEM...

MEMORY SYSTEMS AND METHODS FOR CONTROLLING THE TIMING OF RECEIVING...

SWITCHED INTERFACE STACKED-DIE MEMORY ARCHITECTURE

MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYST...

STACKED DEVICE REMAPPING AND REPAIR

MEMORY SYSTEMS AND METHODS FOR CONTROLLING THE TIMING OF RECEIVING...

SYSTEM AND METHOD FOR CONTROLLING TIMING OF OUTPUT SIGNALS

SYSTEM AND METHOD FOR READ SYNCHRONIZATION OF MEMORY MODULES

STACKED DEVICE REMAPPING AND REPAIR

SWITCHED INTERFACE STACKED-DIE MEMORY ARCHITECTURE

STROBE APPARATUS, SYSTEMS, AND METHODS

MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYST...

MULTI-SERIAL INTERFACE STACKED-DIE MEMORY ARCHITECTURE

SYSTEM AND METHOD FOR CONTROLLING TIMING OF OUTPUT SIGNALS

MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYST...

SYSTEM AND METHOD FOR CONTROLLING TIMING OF OUTPUT SIGNALS

STACKED DEVICE REMAPPING AND REPAIR

CAPTURING READ DATA

STROBE APPARATUS, SYSTEMS, AND METHODS

MEMORY DEVICES WITH BUFFERED COMMAND ADDRESS BUS