Paul Eric Dahlen

Person

Rochester, MN, US

People

Patents Grantslast 30 patents

Information Patent Grant
Surface mount device placement to control a signal path in a printe...
- Patent number 11,439,015
- Issue date Sep 6, 2022
- International Business Machines Corporation
- Layne A. Berge
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Continuity check monitoring for microchip exploitation detection
- Patent number 9,003,559
- Issue date Apr 7, 2015
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signal quality monitoring to defeat microchip exploitation
- Patent number 8,332,659
- Issue date Dec 11, 2012
- International Business Machines Corporation
- Gerald K Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Resistance sensing for defeating microchip exploitation
- Patent number 8,214,657
- Issue date Jul 3, 2012
- International Business Machines Corporation
- Gerald K Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Doped implant monitoring for microchip tamper detection
- Patent number 8,172,140
- Issue date May 8, 2012
- International Business Machines Corporation
- Gerald K Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhanced architectural interconnect options enabled with flipped di...
- Patent number 8,174,103
- Issue date May 8, 2012
- International Business Machines Corporation
- Gerald Keith Bartley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of enhancing on-chip inductance structure utilizing silicon...
- Patent number 8,079,134
- Issue date Dec 20, 2011
- International Business Machines Corporation
- Andrew Benson Maki
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Implementing tamper evident and resistant detection through modulat...
- Patent number 7,989,918
- Issue date Aug 2, 2011
- International Business Machines Corporation
- Gerald Keith Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing enhanced wiring capability for electronic laminate pac...
- Patent number 7,954,081
- Issue date May 31, 2011
- International Business Machines Corporation
- Gerald Keith Bartley
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Capacitance-based microchip exploitation detection
- Patent number 7,952,478
- Issue date May 31, 2011
- International Business Machines Corporation
- Gerald K Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus, and computer program for implementing vertically coupled...
- Patent number 7,945,883
- Issue date May 17, 2011
- International Business Machines Corporation
- Gerald Keith Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Capacitance structures for defeating microchip tampering
- Patent number 7,884,625
- Issue date Feb 8, 2011
- International Business Machines Corporation
- Gerald K. Bartley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for implementing redundant memory access using...
- Patent number 7,882,479
- Issue date Feb 1, 2011
- International Business Machines Corporation
- Gerald Keith Bartley
- G11 - INFORMATION STORAGE
Information Patent Grant
Implementing at-speed Wafer Final Test (WFT) with complete chip cov...
- Patent number 7,852,103
- Issue date Dec 14, 2010
- International Business Machines Corporation
- Gerald Keith Bartley
- G01 - MEASURING TESTING
Information Patent Grant
Computer system having an apportionable data bus and daisy chained...
- Patent number 7,844,769
- Issue date Nov 30, 2010
- International Business Machines Corporation
- Gerald Keith Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and structure for dispensing chip underfill through an openi...
- Patent number 7,838,336
- Issue date Nov 23, 2010
- International Business Machines Corporation
- Gerald K. Bartley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for implementing optimized creation of openings f...
- Patent number 7,810,065
- Issue date Oct 5, 2010
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Implementing decoupling capacitors with hot-spot thermal reduction...
- Patent number 7,723,816
- Issue date May 25, 2010
- International Business Machines Corporation
- Gerald Keith Bartley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Implementing redundant memory access using multiple controllers on...
- Patent number 7,725,762
- Issue date May 25, 2010
- International Business Machines Corporation
- Gerald Keith Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
False connection for defeating microchip exploitation
- Patent number 7,701,244
- Issue date Apr 20, 2010
- International Business Machines Corporation
- Gerald K Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and structure for connecting, stacking, and cooling chips on...
- Patent number 7,675,164
- Issue date Mar 9, 2010
- International Business Machines Corporation
- Gerald Keith Bartley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Computer system having daisy chained memory chips
- Patent number 7,673,093
- Issue date Mar 2, 2010
- International Business Machines Corporation
- Gerald Keith Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for providing switchable decoupling capacitors for an in...
- Patent number 7,667,487
- Issue date Feb 23, 2010
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Daisy chainable self timed memory chip
- Patent number 7,660,942
- Issue date Feb 9, 2010
- International Business Machines Corporation
- Gerald Keith Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Carrier having daisy chain of self timed memory chips
- Patent number 7,660,940
- Issue date Feb 9, 2010
- International Business Machines Corporation
- Gerald Keith Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Spider web interconnect topology utilizing multiple port connection
- Patent number 7,650,455
- Issue date Jan 19, 2010
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller for daisy chained memory chips
- Patent number 7,627,711
- Issue date Dec 1, 2009
- International Business Machines Corporation
- Gerald Keith Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory chip having an apportionable data bus
- Patent number 7,620,763
- Issue date Nov 17, 2009
- International Business Machines Corporation
- Gerald Keith Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Carrier having daisy chained memory chips
- Patent number 7,617,350
- Issue date Nov 10, 2009
- International Business Machines Corporation
- Gerald Keith Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller for daisy chained self timed memory chips
- Patent number 7,577,811
- Issue date Aug 18, 2009
- International Business Machines Corporation
- Gerald Keith Bartley
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SURFACE MOUNT DEVICE PLACEMENT TO CONTROL A SIGNAL PATH IN A PRINTE...
- Publication number 20210112661
- Publication date Apr 15, 2021
- International Business Machines Corporation
- LAYNE A. BERGE
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
SPUR DETECTION IN A SAMPLED WAVEFORM IN A MIXED ANALOG/DIGITAL SYST...
- Publication number 20210102977
- Publication date Apr 8, 2021
- International Business Machines Corporation
- TIMOTHY LINDQUIST
- G01 - MEASURING TESTING
Information Patent Application
SPUR DETECTION IN A SAMPLED WAVEFORM IN A MIXED ANALOG/DIGITAL SYST...
- Publication number 20210102976
- Publication date Apr 8, 2021
- International Business Machines Corporation
- TIMOTHY LINDQUIST
- G01 - MEASURING TESTING
Information Patent Application
IMPLEMENTING AT-SPEED WAFER FINAL TEST (WFT) WITH COMPLETE CHIP COV...
- Publication number 20100271046
- Publication date Oct 28, 2010
- International Business Machines Corporation
- Gerald Keith Bartley
- G01 - MEASURING TESTING
Information Patent Application
IMPLEMENTING TAMPER EVIDENT AND RESISTANT DETECTION THROUGH MODULAT...
- Publication number 20100187525
- Publication date Jul 29, 2010
- International Business Machines Corporation
- Gerald Keith Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Implementing Decoupling Capacitors With Hot-Spot Thermal Reduction...
- Publication number 20100032799
- Publication date Feb 11, 2010
- International Business Machines Corporation
- Gerald Keith Bartley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SHIELDED WIREBOND
- Publication number 20100025864
- Publication date Feb 4, 2010
- International Business Machines Corporation
- Mark J. Bailey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Capacitance-Based Microchip Exploitation Detection
- Publication number 20100026506
- Publication date Feb 4, 2010
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Resistance Sensing for Defeating Microchip Exploitation
- Publication number 20100026326
- Publication date Feb 4, 2010
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Signal Quality Monitoring to Defeat Microchip Exploitation
- Publication number 20100031375
- Publication date Feb 4, 2010
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Doped Implant Monitoring for Microchip Tamper Detection
- Publication number 20100025479
- Publication date Feb 4, 2010
- International Business Machines Corporation
- Gerald K Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Interdependent Microchip Functionality for Defeating Exploitation A...
- Publication number 20100026337
- Publication date Feb 4, 2010
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Enhanced On-Chip Inductance Structure Utilizing Silicon Through Via...
- Publication number 20100024202
- Publication date Feb 4, 2010
- Andrew Benson Maki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Capacitance Structures for Defeating Microchip Tampering
- Publication number 20100026313
- Publication date Feb 4, 2010
- International Business Machines Corporation
- Gerald K. Bartley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FALSE CONNECTION FOR DEFEATING MICROCHIP EXPLOITATION
- Publication number 20100026336
- Publication date Feb 4, 2010
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Continuity Check Monitoring for Microchip Exploitation Detection
- Publication number 20100031376
- Publication date Feb 4, 2010
- International Business Machines Corporation
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Implementing Reduced Hot-Spot Thermal Effects for SOI Circuits
- Publication number 20100019385
- Publication date Jan 28, 2010
- International Business Machines Corporation
- Gerald Keith Bartley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
System and Method for Thermal Optimized Chip Stacking
- Publication number 20090305463
- Publication date Dec 10, 2009
- International Business Machines Corporation
- Gerald K. Bartley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Implementing Cache Coherency and Reduced Latency Using Multiple Con...
- Publication number 20090300291
- Publication date Dec 3, 2009
- Gerald Keith Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Implementing Redundant Memory Access Using Multiple Controllers for...
- Publication number 20090300411
- Publication date Dec 3, 2009
- Gerald Keith Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Enhanced Architectural Interconnect Options Enabled With Flipped Di...
- Publication number 20090273098
- Publication date Nov 5, 2009
- Gerald Keith Bartley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF CONNECTING A SERIES OF INTEGRATED DEVICES UTILIZING FLEXI...
- Publication number 20090183364
- Publication date Jul 23, 2009
- International Business Machines Corporation
- Gerald K. Bartley
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Techniques for Providing Switchable Decoupling Capacitors for an In...
- Publication number 20090179669
- Publication date Jul 16, 2009
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPLEMENTING ENHANCED WIRING CAPABILITY FOR ELECTRONIC LAMINATE PAC...
- Publication number 20090138832
- Publication date May 28, 2009
- International Business Machines Corporation
- Gerald Keith Bartley
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
METHOD AND STRUCTURE FOR DISPENSING CHIP UNDERFILL THROUGH AN OPENI...
- Publication number 20090079060
- Publication date Mar 26, 2009
- GERALD K. BARTLEY
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS TO TEST ELECTRICAL CONTINUITY AND REDUCE LOADI...
- Publication number 20090058425
- Publication date Mar 5, 2009
- International Business Machines Corporation
- Gerald K. Bartley
- G01 - MEASURING TESTING
Information Patent Application
System and Method for Implementing Optimized Creation of Openings f...
- Publication number 20090055134
- Publication date Feb 26, 2009
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Spider Web Interconnect Topology Utilizing Multiple Port Connection
- Publication number 20090031067
- Publication date Jan 29, 2009
- Gerald K. Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Implementing Redundant Memory Access Using...
- Publication number 20080307253
- Publication date Dec 11, 2008
- International Business Machines Corporation
- Gerald Keith Bartley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Implementing Redundant Memory Access Using...
- Publication number 20080307252
- Publication date Dec 11, 2008
- Gerald Keith Bartley
- G06 - COMPUTING CALCULATING COUNTING

Paul Eric Dahlen

Person

Patents Grantslast 30 patents

Surface mount device placement to control a signal path in a printe...

Continuity check monitoring for microchip exploitation detection

Signal quality monitoring to defeat microchip exploitation

Resistance sensing for defeating microchip exploitation

Doped implant monitoring for microchip tamper detection

Enhanced architectural interconnect options enabled with flipped di...

Method of enhancing on-chip inductance structure utilizing silicon...

Implementing tamper evident and resistant detection through modulat...

Implementing enhanced wiring capability for electronic laminate pac...

Capacitance-based microchip exploitation detection

Apparatus, and computer program for implementing vertically coupled...

Capacitance structures for defeating microchip tampering

Method and apparatus for implementing redundant memory access using...

Implementing at-speed Wafer Final Test (WFT) with complete chip cov...

Computer system having an apportionable data bus and daisy chained...

Method and structure for dispensing chip underfill through an openi...

System and method for implementing optimized creation of openings f...

Implementing decoupling capacitors with hot-spot thermal reduction...

Implementing redundant memory access using multiple controllers on...

False connection for defeating microchip exploitation

Method and structure for connecting, stacking, and cooling chips on...

Computer system having daisy chained memory chips

Techniques for providing switchable decoupling capacitors for an in...

Daisy chainable self timed memory chip

Carrier having daisy chain of self timed memory chips

Spider web interconnect topology utilizing multiple port connection

Memory controller for daisy chained memory chips

Memory chip having an apportionable data bus

Carrier having daisy chained memory chips

Memory controller for daisy chained self timed memory chips

Patents Applicationslast 30 patents

SURFACE MOUNT DEVICE PLACEMENT TO CONTROL A SIGNAL PATH IN A PRINTE...

SPUR DETECTION IN A SAMPLED WAVEFORM IN A MIXED ANALOG/DIGITAL SYST...

SPUR DETECTION IN A SAMPLED WAVEFORM IN A MIXED ANALOG/DIGITAL SYST...

IMPLEMENTING AT-SPEED WAFER FINAL TEST (WFT) WITH COMPLETE CHIP COV...

IMPLEMENTING TAMPER EVIDENT AND RESISTANT DETECTION THROUGH MODULAT...

Implementing Decoupling Capacitors With Hot-Spot Thermal Reduction...

SHIELDED WIREBOND

Capacitance-Based Microchip Exploitation Detection

Resistance Sensing for Defeating Microchip Exploitation

Signal Quality Monitoring to Defeat Microchip Exploitation

Doped Implant Monitoring for Microchip Tamper Detection

Interdependent Microchip Functionality for Defeating Exploitation A...

Enhanced On-Chip Inductance Structure Utilizing Silicon Through Via...

Capacitance Structures for Defeating Microchip Tampering

FALSE CONNECTION FOR DEFEATING MICROCHIP EXPLOITATION

Continuity Check Monitoring for Microchip Exploitation Detection

Implementing Reduced Hot-Spot Thermal Effects for SOI Circuits

System and Method for Thermal Optimized Chip Stacking

Implementing Cache Coherency and Reduced Latency Using Multiple Con...

Implementing Redundant Memory Access Using Multiple Controllers for...

Enhanced Architectural Interconnect Options Enabled With Flipped Di...

METHOD OF CONNECTING A SERIES OF INTEGRATED DEVICES UTILIZING FLEXI...

Techniques for Providing Switchable Decoupling Capacitors for an In...

IMPLEMENTING ENHANCED WIRING CAPABILITY FOR ELECTRONIC LAMINATE PAC...

METHOD AND STRUCTURE FOR DISPENSING CHIP UNDERFILL THROUGH AN OPENI...

METHOD AND APPARATUS TO TEST ELECTRICAL CONTINUITY AND REDUCE LOADI...

System and Method for Implementing Optimized Creation of Openings f...

Spider Web Interconnect Topology Utilizing Multiple Port Connection

Method and Apparatus for Implementing Redundant Memory Access Using...

Method and Apparatus for Implementing Redundant Memory Access Using...