1. Field of the Invention
The present invention relates to a system and method for stacking integrated circuits or chips. Specifically, the present invention relates to a system and method for thermal optimization in stacked chips.
2. Description of Background
Integrated circuit or chip manufacturers use chip stacks in order to build more powerful devices. For example, packaged integrated circuit devices, i.e., chips, including, for example, microprocessors, memory devices are stacked together, e.g., back-to-front or back-to-back. Chip stacks are beneficial because they allow more compact circuit arrangements and, therefore, more efficient use of space, e.g., on circuit boards. The advent of thru-silicon via on three-dimensional chip-stacking as a packaging approach has opened up opportunities for creating more compact functions than ever before. Stacks of chips have been demonstrated with greater than ten chips in the stack.
Those with ordinary skill in the art will recognize the electrical advantages of chip stacking. One challenge of stacking chips is thermal management. When the stack of chips is in use, the chips will generate heat. Specifically, chip stacks with a greater number of chips create problems with cooling. Because the chip stacks contain multiple chips, the stacks generate more heat per unit volume. If such heat is not dissipated out of the chip stack, technical issues may occur. In most package approaches, heat will be extracted out of the top of the stack and/or out of the bottom of the stack, usually to a lesser degree. Getting the “heat” out of the die in the middle of the stack is generally recognized as a large challenge.
Further complicating this challenge is the fact that most functions implemented in silicon do not have a uniform power dissipation density. Hence, hot spots are formed where the activity of a macro, e.g., a processor, is significantly higher than other areas of the chip, e.g., a memory array or random logic. Hot spots may form where a segment of the silicon is, for example, 10, 15, or even 20 degrees Celsius, hotter than the surrounding areas.
Stacking multiple chips of the same type will increase the hot spot effect in a 3-dimensional manner. Specifically, if multiple die are stacked on-top of each other, the individual silicon layers may have their hot spots aligned directly above and below each other. This may create additional heating effects and cause the hot spots to be even more pronounced relative to the rest of the silicon surface area in the stack.
One solution is to rotate the die in a stack by wire-bond. This is generally done for memory devices has a much more uniform power dissipation density than that of logic or analog functions. However, wire bonding is not practical to allow the rotation of the bus interface along with the die rotation and is not very effective in large chip stacks because the bonds get long, degrading signal and power integrity.
A method for thermal optimization comprising the steps of stacking a first chip layer and a second chip layer wherein the second chip layer is rotated in relation to the first chip layer wherein a first hot spot on the first chip layer and a second hot spot on the second chip layer are not spatially aligned; routing a signal input through the first chip layer from a first chip pad on the first chip layer to a first silicon via so as to form a physical input to output twist and a first signal output; and routing the first signal output from the first chip layer through a second chip layer from a second chip pad on the second chip layer to a second silicon via so as to form a second signal output.
The present invention is generally directed at providing a low cost solution for dissipating heat generated within chip stacks.
The approach disclosed here is a rotation of the die in concert with thru-silicon via and stacks of flip-chip devices with non-uniform power dissipation.
Using the flexibility of thru-silicon via technology, a method for creating a more uniform power density by distributing the hot spots of an individual layer in a chip stack is created. This reduces the impact of the hot spots on adjacent layers within the stack, and thus reduces the magnitude between the average temperature on the die and the hot spots.
The present invention is advantageous over previous solutions because the chips used on each of the layers may be identical, therefore creating no additional production costs.
The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
The detailed description explains the preferred embodiments of the invention, together with advantages and features, by way of example with reference to the drawings.
Those of ordinary skill in the art will recognize that chip stack 100 may include more than the exemplified two chips. In addition, it will be understood that each of the chips include other components such as memory 103a and 103b, memory controls 104a and 104b, and other logic components. Furthermore, it will be understood that hot spots 102a and 102b may be created by elements in the chip other than the processor cores.
Each chip layer added to the chip stack is rotated such that the hot spots are not lying directly above and below each other or otherwise spatially aligned. For example, as shown in
In a preferred embodiment, the standard metal layer may be used to route the bus from the signal inside to the signal outside. This embodiment keeps the routing internal to the chip wiring layer, e.g., on the same layer as the C4 connectors and on the bottom of the chip. In another preferred embodiment of the present invention, a new layer of metal may be added to route wires through the bus router. In this embodiment, the routing is performed on the back side of the chip.
The diagrams depicted herein are just examples. There may be many variations to these diagrams or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order, or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention.
While the preferred embodiment to the invention has been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.