Patent Application
20090058425
IBM® is a registered trademark of International Business Machines Corporation, Armonk, N.Y., U.S.A. Other names used herein may be registered trademarks, trademarks or product names of International Business Machines Corporation or other companies.
1. Field of the Invention
This invention relates to a method and apparatus for testing electrical continuity in a printed circuit board (PCB) assembly, and particularly to test electrical contact substantially on a top surface of a printed wiring board using probes inserted through holes from a backside of the printed wiring board.
2. Description of Background
A direct current (DC) continuity check is performed to ensure correct component attachment to the PCB during PCB assembly. The DC continuity test is typically done by contacting test probes to the plated-thru vias near components. However, this requires a connection path to be available from all topside attached components to the bottom side in-order to test the assembly entirely from the bottom side of the structure.
Alternatively, testing of the component via a backside probe is avoided altogether, and thus a plated via is not necessary. Although this approach solves the signal degradation problem, it introduces a potential yield/shipped product quality level (SPQL) problem since the component and the related circuit connections are not tested.
Other solutions to the above described problem include using roving/flying-head probes or post-reflow optical inspection. These techniques can test for proper component attachment to the PCB without requiring a plated via corresponding to the surface mounted components. However, these technique has a much slower throughput and increases the cost of testing when compared to “bed of nails” testing. Therefore, use of roving/flying-head probes or post-reflow optical inspection are not desired to test component attachment for high-volume suppliers.
Yet another solution to the plated via include back drilling the plated vias after testing to eliminate the capacitive stub effects. However, this approach too proves to be more costly, slower and adds additional processing steps when compared to “bed of nails” testing.
Still another solution includes changing the PCB layout. For example, the signals could be routed on the bottom side of the PCB, then routed to the topside of the PCB where the component is attached and then routed back down to the bottom side of the PCB. However, this approach too degrades signal integrity and is not always permitted in the particular board layout/route.
Therefore, a need still exists to enhance the “bed of nails” approach to PCB assembly testing that maintains test coverage and does not degrade signal quality.
The shortcomings of the prior art are overcome and additional advantages are provided through the provision of an apparatus for testing electrical continuity of a surface mounted (SMT) electrical board. The apparatus includes: a printed wiring board having a first surface and an opposite second surface; a conductive signal line disposed on each of the first and second surfaces of the printed wiring board; an electrical component disposed on and electrically connected to the conductive signal line on the first surface; and a through hole extending through the printed wiring board and the conductive signal line on the second surface of the printed wiring board exposing a surface side of the conductive signal line facing the first surface of the printed wiring board. The through hole is unplated in an inside bore defining the through hole and the through hole allows direct access to the conductive signal line on the first surface to test continuity of the conductive signal line on the first surface connected to the electrical component from the second surface of the printed wiring board.
In another embodiment, a method for testing electrical continuity of a surface mounted (SMT) electrical board is provided. The method includes: disposing a conductive signal line on a first surface and an opposite second surface of a printed wiring board; extending a through hole through the printed wiring board and the conductive signal line on the second surface of the printed wiring board thereby exposing a surface side facing the first surface of the printed wiring board; masking the through hole to prevent plating of the through hole; plating the first and second surfaces of the printed wiring board; and surface mounting an electrical component to the first surface of the printed wiring board to electrically connect the electrical component to the conductive signal line on the first surface. The through hole is unplated in an inside bore defining the through hole and the through hole allows direct access to the conductive signal line on the first surface to test continuity of the conductive signal line on the first surface connected to the electrical component from the second surface of the printed wiring board.
Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with advantages and features, refer to the description and to the drawings.
The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
The detailed description explains the preferred embodiments of the invention, together with advantages and features, by way of example with reference to the drawings.
Turning now to the drawings in greater detail, it will be seen that
Referring to
The through hole 100 is unplated in an inside bore defining the through hole 100 and the bore has a diameter small enough to allow access to test continuity of the conductive signal line 116 connected to the electrical component 118 from the second surface 134 of the printed wiring board 112. A miniature probe or microprobe 130 as shown in
The small diameter through hole 100 in combination with the smaller probe 130 enables testing of components 118 underneath or shadowed by other components where the frequency of operation for that signal would be adversely affected by the typical via stub illustrated in
In an alternative exemplary embodiment and referring to
Referring now to
In an alternative exemplary embodiment, it will be recognized that an end portion of one of the probes 120 as illustrated in the array of probes of
Referring now to
Surface mounting the electrical component 118 at terminal portions 147 of the conductive signal line 116 on the first surface 132 of the printed wiring board 112 includes solder screen pasting generally indicated with solder 150, placing the electrical component 118 for electrical connection at the terminal portions 147 and reflowing the solder 150.
The through hole 100 is configured having a small enough diameter during raw card processing such that the walls defining the diameter of the through hole 100 are not plated during plating, solder paste screening and reflow, thus preventing seepage of conductive material into the through hole 100. By limiting seepage of the conductive material into the through hole 100, the formation of parasitic capacitance or a capacitive stub is eliminated or effectively reduced.
The through hole 100 is left unplated in an inside bore defining the through hole, allowing access to test electrical continuity of the conductive signal line 116 through the electrical component 118 connected thereto, thereby testing for proper component attachment to the board 112. Proper component attachment can be tested from the second surface 134 of the printed wiring board 112.
Another embodiment of the process to create the unplated hole 100 is to use an excimer laser (not shown) after plating the first and second surfaces 132 and 134 of the board 112. The excimer laser removes dielectric material but will not remove copper. In this alternative embodiment, the process is similar to the method described above, but ensures that no copper covered bottom side access to the topside trace (e.g., a copper ‘antipad’ is inserted into the CAD of the board design during layout). Once the plating is completed, the excimer laser is utilized to create the unplated hole 100 allowing for bottom side access to the topside trace to test for proper component attachment.
In either method, a small hole is created where contact to a topside trace is desired. During raw card processing, the walls defining this through hole 100 are not plated. The unplated holes 100 do not have parasitic capacitance normally associated with vias. The hole 100 is small enough such that during plating, solder paste screening, and reflow, the seepage of conductive material into the hole is minimal. During “bed of nails” testing, which tests for proper component connection, a small probe is inserted through the hole 100 and contacts the bottom of the metal pad/trace on the topside surface, thus allowing contact from the bottom side of the board to the topside component/trace.
It will be recognized by those skilled in the pertinent art that although the exemplary embodiments described above pertain to solder connection, the present invention is not limited thereto. For example, the present invention may be used with land grid array (LGA), temporary chip attachment (TCA), or other attach approach in addition to a soldered connection.
In the above described embodiments, the additional small probing hole does not plate significantly far down into the PCB, if at all. The small probing hole is dimensioned such that it is not plated during the plating process, and is small enough such that solder will not wick down the hole. In addition, a solder mask tent and/or dam may be used to prevent solder from entering the hole in the first place. Moreover, as discussed above, the above described probing technique is not necessarily limited to applications where solder attach is used. Although the prior art often uses simply DC test stimulus, as we discuss in the present the invention, it will be recognized by those skilled in the art the alternating current (AC) testing, including time domain reflectometry (TDR), vector network analyzers (VNA), and other ratio type measurements may be facilitated
While the preferred embodiments to the invention have been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.
