Paul Packan

Person

Beaverton, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
Diffused tip extension transistor
- Patent number 11,664,452
- Issue date May 30, 2023
- Intel Corporation
- Pratik A. Patel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS varactor with increased tuning range
- Patent number 11,264,517
- Issue date Mar 1, 2022
- Intel Corporation
- Mohammed El-Tanani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Diffused tip extension transistor
- Patent number 10,872,977
- Issue date Dec 22, 2020
- Intel Corporation
- Pratik A. Patel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Diffused tip extension transistor
- Patent number 10,304,956
- Issue date May 28, 2019
- Intel Corporation
- Pratik A. Patel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Field effect transistor structure with abrupt source/drain junctions
- Patent number 9,793,373
- Issue date Oct 17, 2017
- Intel Corporation
- Anand S. Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Field effect transistor structure with abrupt source/drain junctions
- Patent number 9,640,634
- Issue date May 2, 2017
- Intel Corporation
- Anand S. Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS fabrication process utilizing special transistor orientation
- Patent number 7,888,710
- Issue date Feb 15, 2011
- Intel Corporation
- Mark Armstrong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Field effect transistor structure with abrupt source/drain junctions
- Patent number 7,682,916
- Issue date Mar 23, 2010
- Intel Corporation
- Anand S. Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a field effect transistor structure with abru...
- Patent number 7,436,035
- Issue date Oct 14, 2008
- Intel Corporation
- Anand S. Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a field effect transistor structure with abru...
- Patent number 7,338,873
- Issue date Mar 4, 2008
- Intel Corporation
- Anand S. Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS fabrication process utilizing special transistor orientation
- Patent number 7,312,485
- Issue date Dec 25, 2007
- Intel Corporation
- Mark Armstrong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nitrogen controlled growth of dislocation loop in stress enhanced t...
- Patent number 7,226,824
- Issue date Jun 5, 2007
- Intel Corporation
- Cory E. Weber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nitrogen controlled growth of dislocation loop in stress enhanced t...
- Patent number 7,187,057
- Issue date Mar 6, 2007
- Intel Corporation
- Cory E. Weber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a field effect transistor structure with abru...
- Patent number 6,887,762
- Issue date May 3, 2005
- Intel Corporation
- Anand S. Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Nitrogen controlled growth of dislocation loop in stress enhanced t...
- Patent number 6,800,887
- Issue date Oct 5, 2004
- Intel Corporation
- Cory E. Weber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor with ultra shallow tip and method of fabrication
- Patent number 6,326,664
- Issue date Dec 4, 2001
- Intel Corporation
- Robert S. Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor with minimal junction capacitance and method of fabrication
- Patent number 6,198,142
- Issue date Mar 6, 2001
- Intel Corporation
- Robert S. Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Channel dopant implantation with automatic compensation for variati...
- Patent number 6,020,244
- Issue date Feb 1, 2000
- Intel Corporation
- Scott E. Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low damage doping technique for self-aligned source and drain regions
- Patent number 5,976,939
- Issue date Nov 2, 1999
- Intel Corporation
- Scott Thompson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a transistor
- Patent number 5,908,313
- Issue date Jun 1, 1999
- Intel Corporation
- Robert S. Chau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistor with ultra shallow tip and method of fabrication
- Patent number 5,710,450
- Issue date Jan 20, 1998
- Intel Corporation
- Robert S. Chau
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
PERFORMANCE OPTIMIZATION OF TRANSISTORS SHARING CHANNEL STRUCTURES...
- Publication number 20250006734
- Publication date Jan 2, 2025
- Intel Corporation
- Tao Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT DEVICE WITH REDUCED N-P BOUNDARY EFFECT
- Publication number 20240321887
- Publication date Sep 26, 2024
- Intel Corporation
- Tao Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT DEVICE WITH PERFORMANCE-ENHANCING LAYOUT
- Publication number 20240321859
- Publication date Sep 26, 2024
- Intel Corporation
- Tao Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ULTRA-LOW VOLTAGE TRANSISTOR CELL DESIGN USING GATE CUT LAYOUT
- Publication number 20240113118
- Publication date Apr 4, 2024
- Intel Corporation
- Tao Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE PERFORMANCE TUNING BY DEEP TRENCH VIA (DVB) PROXIMITY EFFECT...
- Publication number 20230317594
- Publication date Oct 5, 2023
- Tao CHU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIFFUSED TIP EXTENSION TRANSISTOR
- Publication number 20230253499
- Publication date Aug 10, 2023
- Intel Corporation
- Pratik A. PATEL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIFFUSED TIP EXTENSION TRANSISTOR
- Publication number 20210050448
- Publication date Feb 18, 2021
- Intel Corporation
- Pratik A. PATEL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIFFUSED TIP EXTENSION TRANSISTOR
- Publication number 20190245088
- Publication date Aug 8, 2019
- Intel Corporation
- Pratik A. PATEL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS VARACTOR WITH INCREASED TUNING RANGE
- Publication number 20170330977
- Publication date Nov 16, 2017
- Intel Corporation
- MOHAMMED EL-TANANI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIELD EFFECT TRANSISTOR STRUCTURE WITH ABRUPT SOURCE/DRAIN JUNCTIONS
- Publication number 20170186855
- Publication date Jun 29, 2017
- Intel Corporation
- Anand S. Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIFFUSED TIP EXTENSION TRANSISTOR
- Publication number 20160380102
- Publication date Dec 29, 2016
- Intel Corporation
- Pratik A. PATEL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FIELD EFFECT TRANSISTOR STRUCTURE WITH ABRUPT SOURCE/DRAIN JUNCTIONS
- Publication number 20100133595
- Publication date Jun 3, 2010
- Anand S. Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High voltage compliant apparatus for semiconductor fabrication proc...
- Publication number 20090323235
- Publication date Dec 31, 2009
- Sangwoo Pae
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Field effect transistor structure with abrupt source/drain junctions
- Publication number 20090011565
- Publication date Jan 8, 2009
- Anand S. Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS FABRICATION PROCESS UTILIZING SPECIAL TRANSISTOR ORIENTATION
- Publication number 20080036005
- Publication date Feb 14, 2008
- Mark Armstrong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of fabricating a field effect transistor structure with abru...
- Publication number 20060220153
- Publication date Oct 5, 2006
- Anand S. Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Nitrogen controlled growth of dislocation loop in stress enhanced t...
- Publication number 20050017309
- Publication date Jan 27, 2005
- Cory E. Weber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of fabricating a field effect transistor structure with abru...
- Publication number 20050012146
- Publication date Jan 20, 2005
- Anand S. Murthy
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Nitrogen controlled growth of dislocation loop in stress enhanced t...
- Publication number 20050014351
- Publication date Jan 20, 2005
- Cory E. Weber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
NITROGEN CONTROLLED GROWTH OF DISLOCATION LOOP IN STRESS ENHANCED T...
- Publication number 20040191975
- Publication date Sep 30, 2004
- Cory E. Weber
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CMOS fabrication process utilizing special transistor orientation
- Publication number 20020063292
- Publication date May 30, 2002
- Mark Armstrong
- H01 - BASIC ELECTRIC ELEMENTS

Paul Packan

Person

Patents Grantslast 30 patents

Diffused tip extension transistor

CMOS varactor with increased tuning range

Diffused tip extension transistor

Diffused tip extension transistor

Field effect transistor structure with abrupt source/drain junctions

Field effect transistor structure with abrupt source/drain junctions

CMOS fabrication process utilizing special transistor orientation

Field effect transistor structure with abrupt source/drain junctions

Method of fabricating a field effect transistor structure with abru...

Method of fabricating a field effect transistor structure with abru...

CMOS fabrication process utilizing special transistor orientation

Nitrogen controlled growth of dislocation loop in stress enhanced t...

Nitrogen controlled growth of dislocation loop in stress enhanced t...

Method of fabricating a field effect transistor structure with abru...

Nitrogen controlled growth of dislocation loop in stress enhanced t...

Transistor with ultra shallow tip and method of fabrication

Transistor with minimal junction capacitance and method of fabrication

Channel dopant implantation with automatic compensation for variati...

Low damage doping technique for self-aligned source and drain regions

Method of forming a transistor

Transistor with ultra shallow tip and method of fabrication

Patents Applicationslast 30 patents

PERFORMANCE OPTIMIZATION OF TRANSISTORS SHARING CHANNEL STRUCTURES...

INTEGRATED CIRCUIT DEVICE WITH REDUCED N-P BOUNDARY EFFECT

INTEGRATED CIRCUIT DEVICE WITH PERFORMANCE-ENHANCING LAYOUT

ULTRA-LOW VOLTAGE TRANSISTOR CELL DESIGN USING GATE CUT LAYOUT

DEVICE PERFORMANCE TUNING BY DEEP TRENCH VIA (DVB) PROXIMITY EFFECT...

DIFFUSED TIP EXTENSION TRANSISTOR

DIFFUSED TIP EXTENSION TRANSISTOR

DIFFUSED TIP EXTENSION TRANSISTOR

CMOS VARACTOR WITH INCREASED TUNING RANGE

FIELD EFFECT TRANSISTOR STRUCTURE WITH ABRUPT SOURCE/DRAIN JUNCTIONS

DIFFUSED TIP EXTENSION TRANSISTOR

FIELD EFFECT TRANSISTOR STRUCTURE WITH ABRUPT SOURCE/DRAIN JUNCTIONS

High voltage compliant apparatus for semiconductor fabrication proc...

Field effect transistor structure with abrupt source/drain junctions

CMOS FABRICATION PROCESS UTILIZING SPECIAL TRANSISTOR ORIENTATION

Method of fabricating a field effect transistor structure with abru...

Nitrogen controlled growth of dislocation loop in stress enhanced t...

Method of fabricating a field effect transistor structure with abru...

Nitrogen controlled growth of dislocation loop in stress enhanced t...

NITROGEN CONTROLLED GROWTH OF DISLOCATION LOOP IN STRESS ENHANCED T...

CMOS fabrication process utilizing special transistor orientation