Pavel Poplevine

Person

Burlingame, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Anti-pirate circuit for protection against commercial integrated ci...
- Patent number RE44130
- Issue date Apr 2, 2013
- National Semiconductor Corporation
- Elroy M. Lucero
- 713 - Electrical computers and digital processing systems: support
Information Patent Grant
All-NMOS 4-transistor non-volatile memory cell
- Patent number 8,363,469
- Issue date Jan 29, 2013
- National Semiconductor Corporation
- Pavel Poplevine
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
5-transistor non-volatile memory cell
- Patent number 8,284,600
- Issue date Oct 9, 2012
- National Semiconductor Corporation
- Pavel Poplevine
- G11 - INFORMATION STORAGE
Information Patent Grant
4-transistor non-volatile memory cell with PMOS-NMOS-PMOS-NMOS stru...
- Patent number 8,213,227
- Issue date Jul 3, 2012
- National Semiconductor Corporation
- Pavel Poplevine
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of directly reading output voltage to determine data stored...
- Patent number 8,159,877
- Issue date Apr 17, 2012
- National Semiconductor Corporation
- Pavel Poplevine
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory cell with improved programming technique with d...
- Patent number 7,656,698
- Issue date Feb 2, 2010
- National Semiconductor Corporation
- Pavel Poplevine
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of making a non-volatile memory (NVM) cell structure and pro...
- Patent number 7,602,641
- Issue date Oct 13, 2009
- National Semiconductor Corporation
- Pavel Poplevine
- G11 - INFORMATION STORAGE
Information Patent Grant
Anti-pirate circuit for protection against commercial integrated ci...
- Patent number 7,558,969
- Issue date Jul 7, 2009
- National Semiconductor Corporation
- Elroy M. Lucero
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-volatile memory cell with improved programming technique and de...
- Patent number 7,453,726
- Issue date Nov 18, 2008
- National Semiconductor Corporation
- Pavel Poplevine
- G11 - INFORMATION STORAGE
Information Patent Grant
Bit line sharing and word line load reduction for low AC power SRAM...
- Patent number 7,286,383
- Issue date Oct 23, 2007
- National Semiconductor Corporation
- Pavel Poplevine
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of hot electron injection programming of a non-volatile memo...
- Patent number 7,239,558
- Issue date Jul 3, 2007
- National Semiconductor Corporation
- Pavel Poplevine
- G11 - INFORMATION STORAGE
Information Patent Grant
Closed-loop, supply-adjusted ROM memory circuit
- Patent number 7,206,959
- Issue date Apr 17, 2007
- National Semiconductor Corporation
- Wai Cheong Chan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-volatile memory cell with improved programming technique
- Patent number 7,167,392
- Issue date Jan 23, 2007
- National Semiconductor Corporation
- Pavel Poplevine
- G11 - INFORMATION STORAGE
Information Patent Grant
Reverse fowler-nordheim tunneling programming for non-volatile memo...
- Patent number 7,164,606
- Issue date Jan 16, 2007
- National Semiconductor Corporation
- Pavel Poplevine
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power ROM architecture
- Patent number 7,126,866
- Issue date Oct 24, 2006
- National Semiconductor Corporation
- Pavel Poplevine
- G11 - INFORMATION STORAGE
Information Patent Grant
Closed-loop, supply-adjusted RAM memory circuit
- Patent number 7,069,461
- Issue date Jun 27, 2006
- National Semiconductor Corporation
- Wai Cheong Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
Low AC power SRAM architecture
- Patent number 7,061,792
- Issue date Jun 13, 2006
- National Semiconductor Corporation
- Pavel Poplevine
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming method for nonvolatile memory cell
- Patent number 7,042,763
- Issue date May 9, 2006
- National Semiconductor Corporation
- Yuri Mirgorodski
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming method for nonvolatile memory cell
- Patent number 7,020,027
- Issue date Mar 28, 2006
- National Semiconductor Corporation
- Pavel Poplevine
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile memory cell
- Patent number 6,992,927
- Issue date Jan 31, 2006
- National Semiconductor Corporation
- Pavel Poplevine
- G11 - INFORMATION STORAGE
Information Patent Grant
Programming method for nonvolatile memory cell
- Patent number 6,985,386
- Issue date Jan 10, 2006
- National Semiconductor Corporation
- Yuri Mirgorodski
- G11 - INFORMATION STORAGE
Information Patent Grant
Static RAM architecture with bit line partitioning
- Patent number 6,711,051
- Issue date Mar 23, 2004
- National Semiconductor Corporation
- Pavel Poplevine
- G11 - INFORMATION STORAGE
Information Patent Grant
High density ROM architecture
- Patent number 6,642,587
- Issue date Nov 4, 2003
- National Semiconductor Corporation
- Pavel Poplevine
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of programming a splity-gate flash memory cell with a positi...
- Patent number 6,621,736
- Issue date Sep 16, 2003
- National Semiconductor Corporation
- Yuri Mirgorodski
- G11 - INFORMATION STORAGE
Information Patent Grant
High density ROM architecture with inversion of programming
- Patent number 6,618,282
- Issue date Sep 9, 2003
- National Semiconductor Corporation
- Pavel Poplevine
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power static RAM architecture
- Patent number 6,563,730
- Issue date May 13, 2003
- National Semiconductor Corporation
- Pavel Poplevine
- G11 - INFORMATION STORAGE
Information Patent Grant
Extended drain MOSFET for programming an integrated fuse element to...
- Patent number 6,525,397
- Issue date Feb 25, 2003
- National Semiconductor Corporation
- Alexander Kalnitsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of an apparatus for programming an integrated fuse element t...
- Patent number 6,420,217
- Issue date Jul 16, 2002
- National Semiconductor Corporation
- Alexander Kalnitsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CMOS compatible pixel cell that utilizes a gated diode to reset the...
- Patent number 6,384,398
- Issue date May 7, 2002
- National Semiconductor Corporation
- Alexander Kalnitsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Schottky diode with reduced size
- Patent number 6,380,054
- Issue date Apr 30, 2002
- National Semiconductor Corporation
- Alexander Kalnitsky
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
3 TRANSISTOR (N/P/N) NON-VOLATILE MEMORY CELL WITHOUT PROGRAM DISTURB
- Publication number 20120014183
- Publication date Jan 19, 2012
- Pavel Poplevine
- G11 - INFORMATION STORAGE
Information Patent Application
4-TRANSISTOR NON-VOLATILE MEMORY CELL WITH PMOS-NMOS-PMOS-NMOS STRU...
- Publication number 20110242898
- Publication date Oct 6, 2011
- Pavel Poplevine
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF DIRECTLY READING OUTPUT VOLTAGE TO DETERMINE DATA STORED...
- Publication number 20110235425
- Publication date Sep 29, 2011
- Pavel Poplevine
- G11 - INFORMATION STORAGE
Information Patent Application
Method of making a non-volatile memory (NVM) cell structure and pro...
- Publication number 20090129162
- Publication date May 21, 2009
- Pavel Poplevine
- G11 - INFORMATION STORAGE

Pavel Poplevine

Person

Patents Grantslast 30 patents

Anti-pirate circuit for protection against commercial integrated ci...

All-NMOS 4-transistor non-volatile memory cell

5-transistor non-volatile memory cell

4-transistor non-volatile memory cell with PMOS-NMOS-PMOS-NMOS stru...

Method of directly reading output voltage to determine data stored...

Non-volatile memory cell with improved programming technique with d...

Method of making a non-volatile memory (NVM) cell structure and pro...

Anti-pirate circuit for protection against commercial integrated ci...

Non-volatile memory cell with improved programming technique and de...

Bit line sharing and word line load reduction for low AC power SRAM...

Method of hot electron injection programming of a non-volatile memo...

Closed-loop, supply-adjusted ROM memory circuit

Non-volatile memory cell with improved programming technique

Reverse fowler-nordheim tunneling programming for non-volatile memo...

Low power ROM architecture

Closed-loop, supply-adjusted RAM memory circuit

Low AC power SRAM architecture

Programming method for nonvolatile memory cell

Programming method for nonvolatile memory cell

Nonvolatile memory cell

Programming method for nonvolatile memory cell

Static RAM architecture with bit line partitioning

High density ROM architecture

Method of programming a splity-gate flash memory cell with a positi...

High density ROM architecture with inversion of programming

Low power static RAM architecture

Extended drain MOSFET for programming an integrated fuse element to...

Method of an apparatus for programming an integrated fuse element t...

CMOS compatible pixel cell that utilizes a gated diode to reset the...

Schottky diode with reduced size

Patents Applicationslast 30 patents

3 TRANSISTOR (N/P/N) NON-VOLATILE MEMORY CELL WITHOUT PROGRAM DISTURB

4-TRANSISTOR NON-VOLATILE MEMORY CELL WITH PMOS-NMOS-PMOS-NMOS STRU...

METHOD OF DIRECTLY READING OUTPUT VOLTAGE TO DETERMINE DATA STORED...

Method of making a non-volatile memory (NVM) cell structure and pro...