Peter Elenius

Person

Scottsdale, AZ, US

People

Patents Grantslast 30 patents

Information Patent Grant
Electronic device package and method for fabricating the same
- Patent number 8,487,437
- Issue date Jul 16, 2013
- Optopac Co., Ltd.
- Peter Elenius
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming a circuit board with improved via design
- Patent number 8,141,245
- Issue date Mar 27, 2012
- PPG Industries Ohio, Inc.
- Kevin C. Olson
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Wafer-level moat structures
- Patent number 7,126,164
- Issue date Oct 24, 2006
- FlipChip International LLC
- Michael E. Johnson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming partial-depth features in polymer film
- Patent number 7,118,833
- Issue date Oct 10, 2006
- FlipChip International, LLC
- Peter Elenius
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Solder bar for high power flip chips
- Patent number 7,057,292
- Issue date Jun 6, 2006
- FlipChip International, LLC
- Peter Elenius
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method for forming chip scale package
- Patent number 6,750,135
- Issue date Jun 15, 2004
- Flip Chip Technologies, L.L.C.
- Peter Elenius
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Polymer collar for solder bumps
- Patent number 6,578,755
- Issue date Jun 17, 2003
- Flip Chip Technologies, L.L.C.
- Peter Elenius
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Chip scale package using large ductile solder balls
- Patent number 6,441,487
- Issue date Aug 27, 2002
- Flip Chip Technologies, L.L.C.
- Peter Elenius
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for forming chip scale package
- Patent number 6,287,893
- Issue date Sep 11, 2001
- Flip Chip Technologies, L.L.C.
- Peter Elenius
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ELECTRONIC DEVICE PACKAGE AND METHOD FOR FABRICATING THE SAME
- Publication number 20110193231
- Publication date Aug 11, 2011
- OPTOPAC CO., LTD.
- Peter ELENIUS
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Single or Multi-Layer Printed Circuit Board With Improved Via Design
- Publication number 20090101274
- Publication date Apr 23, 2009
- Kevin C. Olson
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
CIRCUIT ASSEMBLY INCLUDING A METAL CORE SUBSTRATE AND PROCESS FOR P...
- Publication number 20080302564
- Publication date Dec 11, 2008
- PPG INDUSTRIES OHIO, INC.
- Kevin C. Olson
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Wafer-level moat structures
- Publication number 20050070083
- Publication date Mar 31, 2005
- FLIP CHIP TECHNOLOGIES, L.L.C.
- Michael E. Johnson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Forming partial-depth features in polymer film
- Publication number 20050069782
- Publication date Mar 31, 2005
- FLIP CHIP TECHNOLOGIES, L.L.C.
- Peter Elenius
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Method for forming chip scale package
- Publication number 20010031548
- Publication date Oct 18, 2001
- PETER ELENIUS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHIP SCALE PACKAGE USING LARGE DUCTILE SOLDER BALLS
- Publication number 20010011764
- Publication date Aug 9, 2001
- PETER ELENIUS
- G06 - COMPUTING CALCULATING COUNTING

Peter Elenius

Person

Patents Grantslast 30 patents

Electronic device package and method for fabricating the same

Method of forming a circuit board with improved via design

Wafer-level moat structures

Forming partial-depth features in polymer film

Solder bar for high power flip chips

Method for forming chip scale package

Polymer collar for solder bumps

Chip scale package using large ductile solder balls

Method for forming chip scale package

Patents Applicationslast 30 patents

ELECTRONIC DEVICE PACKAGE AND METHOD FOR FABRICATING THE SAME

Single or Multi-Layer Printed Circuit Board With Improved Via Design

CIRCUIT ASSEMBLY INCLUDING A METAL CORE SUBSTRATE AND PROCESS FOR P...

Wafer-level moat structures

Forming partial-depth features in polymer film

Method for forming chip scale package

CHIP SCALE PACKAGE USING LARGE DUCTILE SOLDER BALLS