Peter G. Tolchinsky

Person

Beaverton, OR, US

People

Patents Grantslast 30 patents

Information Patent Grant
GaN devices on engineered silicon substrates
- Patent number 10,692,839
- Issue date Jun 23, 2020
- Intel Corporation
- Sansaptak Dasgupta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon PMOS with gallium nitride NMOS for voltage regulation
- Patent number 10,600,787
- Issue date Mar 24, 2020
- Intel Corporation
- Sansaptak Dasgupta
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Methods of forming hetero-layers with reduced surface roughness and...
- Patent number 9,711,591
- Issue date Jul 18, 2017
- Intel Corporation
- Niloy Mukherjee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Epitaxial wafer and a method of manufacturing thereof
- Patent number 9,691,632
- Issue date Jun 27, 2017
- Siltronic AG
- Peter Storck
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Common-substrate semiconductor devices having nanowires or semicond...
- Patent number 9,691,843
- Issue date Jun 27, 2017
- Intel Corporation
- Annalisa Cappellani
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Common-substrate semiconductor devices having nanowires or semicond...
- Patent number 9,559,160
- Issue date Jan 31, 2017
- Intel Corporation
- Annalisa Cappellani
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Stacking fault and twin blocking barrier for integrating III-V on Si
- Patent number 8,617,945
- Issue date Dec 31, 2013
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High hole mobility p-channel Ge transistor structure on Si substrate
- Patent number 8,217,383
- Issue date Jul 10, 2012
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Stacking fault and twin blocking barrier for integrating III-V on Si
- Patent number 8,143,646
- Issue date Mar 27, 2012
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dislocation removal from a group III-V film grown on a semiconducto...
- Patent number 7,863,710
- Issue date Jan 4, 2011
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buffer layers for device isolation of devices grown on silicon
- Patent number 7,851,781
- Issue date Dec 14, 2010
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High hole mobility p-channel Ge transistor structure on Si substrate
- Patent number 7,791,063
- Issue date Sep 7, 2010
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming buffer layer architecture on silicon and structu...
- Patent number 7,687,799
- Issue date Mar 30, 2010
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ultra-thin oxide bonding for S1 to S1 dual orientation bonding
- Patent number 7,670,928
- Issue date Mar 2, 2010
- Intel Corporation
- Mohamad A. Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dislocation-free InSb quantum well structure on Si using novel buff...
- Patent number 7,573,059
- Issue date Aug 11, 2009
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual crystal orientation circuit devices on the same substrate
- Patent number 7,569,857
- Issue date Aug 4, 2009
- Intel Corporation
- Peter Tolchinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods and apparatuses for manufacturing ultra thin device layers...
- Patent number 7,531,429
- Issue date May 12, 2009
- Intel Corporation
- Peter Tolchinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buffer layers for device isolation of devices grown on silicon
- Patent number 7,494,911
- Issue date Feb 24, 2009
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Transistors with increased mobility in the channel zone and method...
- Patent number 7,491,988
- Issue date Feb 17, 2009
- Intel Corporation
- Peter G. Tolchinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a silicon-on-insulator (SOI) wafer with an...
- Patent number 7,473,614
- Issue date Jan 6, 2009
- Intel Corporation
- Peter G. Tolchinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of vertically stacking wafers using porous silicon
- Patent number 7,378,331
- Issue date May 27, 2008
- Intel Corporation
- Mohamad Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Complete device layer transfer without edge exclusion via direct wa...
- Patent number 7,161,224
- Issue date Jan 9, 2007
- Intel Corporation
- Peter Tolchinsky
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Methods and apparatuses for manufacturing ultra thin device layers...
- Patent number 7,091,108
- Issue date Aug 15, 2006
- Intel Corporation
- Peter Tolchinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High mobility tri-gate devices and methods of fabrication
- Patent number 7,042,009
- Issue date May 9, 2006
- Intel Corporation
- Mohamad A. Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for making a semiconductor device having increased carrier m...
- Patent number 6,924,543
- Issue date Aug 2, 2005
- Intel Corporation
- Peter G. Tolchinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming silicon on insulator wafers
- Patent number 6,911,380
- Issue date Jun 28, 2005
- Intel Corporation
- Peter G. Tolchinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Complete device layer transfer without edge exclusion via direct wa...
- Patent number 6,908,027
- Issue date Jun 21, 2005
- Intel Corporation
- Peter Tolchinsky
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR

Patents Applicationslast 30 patents

Information Patent Application
SILICON PMOS WITH GALLIUM NITRIDE NMOS FOR VOLTAGE REGULATION
- Publication number 20190051650
- Publication date Feb 14, 2019
- Intel Corporation
- Sansaptak Dasgupta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GAN DEVICES ON ENGINEERED SILICON SUBSTRATES
- Publication number 20180145052
- Publication date May 24, 2018
- Intel Corporation
- Sansaptak DASGUPTA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMMON-SUBSTRATE SEMICONDUCTOR DEVICES HAVING NANOWIRES OR SEMICOND...
- Publication number 20160133735
- Publication date May 12, 2016
- Annalisa CAPPELLANI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EPITAXIAL WAFER AND A METHOD OF MANUFACTURING THEREOF
- Publication number 20150303071
- Publication date Oct 22, 2015
- SILTRONIC AG
- Peter STORCK
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMMON-SUBSTRATE SEMICONDUCTOR DEVICES HAVING NANOWIRES OR SEMICOND...
- Publication number 20130320294
- Publication date Dec 5, 2013
- Annalisa Cappellani
- B82 - NANO-TECHNOLOGY
Information Patent Application
STACKING FAULT AND TWIN BLOCKING BARRIER FOR INTEGRATING III-V ON SI
- Publication number 20120142166
- Publication date Jun 7, 2012
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH HOLE MOBILITY P-CHANNEL GE TRANSISTOR STRUCTURE ON SI SUBSTRATE
- Publication number 20100327261
- Publication date Dec 30, 2010
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Back gate doping for SOI substrates
- Publication number 20100155880
- Publication date Jun 24, 2010
- Intel Corporation
- Ibrahim Ban
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Group III-V devices with delta-doped layer under channel region
- Publication number 20100148153
- Publication date Jun 17, 2010
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods of forming buffer layer architecture on silicon and structu...
- Publication number 20090315018
- Publication date Dec 24, 2009
- Mantu K. Hudait
- B82 - NANO-TECHNOLOGY
Information Patent Application
Buffer layers for device isolation of devices grown on silicon
- Publication number 20090218596
- Publication date Sep 3, 2009
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DISLOCATION REMOVAL FROM A GROUP III-V FILM GROWN ON A SEMICONDUCTO...
- Publication number 20090206324
- Publication date Aug 20, 2009
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for manufacturing a silicon-on-insulator (SOI) wafer with an...
- Publication number 20090096025
- Publication date Apr 16, 2009
- Peter G. Tolchinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL SEMICONDUCTOR WAFER CARRIER
- Publication number 20090071918
- Publication date Mar 19, 2009
- Panchapakesan Ramanarayanan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High Hole Mobility P-Channel Ge Transistor Structure on Si Substrate
- Publication number 20090057648
- Publication date Mar 5, 2009
- Intel Corporation
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Ultra-thin oxide bonding for S1 to S1 dual orientation bonding
- Publication number 20080099839
- Publication date May 1, 2008
- Willy Rachmady
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual crystal orientation circuit devices on the same substrate
- Publication number 20080079003
- Publication date Apr 3, 2008
- Mohamad A. Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dislocation-free InSb quantum well structure on Si using novel buff...
- Publication number 20080073639
- Publication date Mar 27, 2008
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Buffer layers for device isolation of devices grown on silicon
- Publication number 20080076235
- Publication date Mar 27, 2008
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Stacking fault and twin blocking barrier for integrating III-V on Si
- Publication number 20080032478
- Publication date Feb 7, 2008
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Depositing polar materials on non-polar semiconductor substrates
- Publication number 20070238281
- Publication date Oct 11, 2007
- Mantu K. Hudait
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Insulation layer for silicon-on-insulator wafer
- Publication number 20070063279
- Publication date Mar 22, 2007
- Peter G. Tolchinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods and apparatuses for manufacturing ultra thin device layers...
- Publication number 20060177994
- Publication date Aug 10, 2006
- Peter Tolchinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods of vertically stacking wafers using porous silicon
- Publication number 20060138627
- Publication date Jun 29, 2006
- Mohamad Shaheen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for manufacturing a silicon-on-Insulator (SOI) wafer with an...
- Publication number 20060102988
- Publication date May 18, 2006
- Peter G. Tolchinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Transistors with increased mobility in the channel zone and method...
- Publication number 20050285212
- Publication date Dec 29, 2005
- Peter G. Tolchinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor wafers with non-standard crystal orientations and met...
- Publication number 20050217560
- Publication date Oct 6, 2005
- Peter G. Tolchinsky
- C30 - CRYSTAL GROWTH
Information Patent Application
Complete device layer transfer without edge exclusion via direct wa...
- Publication number 20050173781
- Publication date Aug 11, 2005
- Peter Tolchinsky
- B23 - MACHINE TOOLS METAL-WORKING NOT OTHERWISE PROVIDED FOR
Information Patent Application
Devices and methods employing high thermal conductivity heat dissip...
- Publication number 20050070048
- Publication date Mar 31, 2005
- Peter G. Tolchinsky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods and apparatuses for manufacturing ultra thin device layers...
- Publication number 20050059221
- Publication date Mar 17, 2005
- Peter Tolchinsky
- H01 - BASIC ELECTRIC ELEMENTS

Peter G. Tolchinsky

Person

Patents Grantslast 30 patents

GaN devices on engineered silicon substrates

Silicon PMOS with gallium nitride NMOS for voltage regulation

Methods of forming hetero-layers with reduced surface roughness and...

Epitaxial wafer and a method of manufacturing thereof

Common-substrate semiconductor devices having nanowires or semicond...

Common-substrate semiconductor devices having nanowires or semicond...

Stacking fault and twin blocking barrier for integrating III-V on Si

High hole mobility p-channel Ge transistor structure on Si substrate

Stacking fault and twin blocking barrier for integrating III-V on Si

Dislocation removal from a group III-V film grown on a semiconducto...

Buffer layers for device isolation of devices grown on silicon

High hole mobility p-channel Ge transistor structure on Si substrate

Methods of forming buffer layer architecture on silicon and structu...

Ultra-thin oxide bonding for S1 to S1 dual orientation bonding

Dislocation-free InSb quantum well structure on Si using novel buff...

Dual crystal orientation circuit devices on the same substrate

Methods and apparatuses for manufacturing ultra thin device layers...

Buffer layers for device isolation of devices grown on silicon

Transistors with increased mobility in the channel zone and method...

Method for manufacturing a silicon-on-insulator (SOI) wafer with an...

Methods of vertically stacking wafers using porous silicon

Complete device layer transfer without edge exclusion via direct wa...

Methods and apparatuses for manufacturing ultra thin device layers...

High mobility tri-gate devices and methods of fabrication

Method for making a semiconductor device having increased carrier m...

Method of forming silicon on insulator wafers

Complete device layer transfer without edge exclusion via direct wa...

Patents Applicationslast 30 patents

SILICON PMOS WITH GALLIUM NITRIDE NMOS FOR VOLTAGE REGULATION

GAN DEVICES ON ENGINEERED SILICON SUBSTRATES

COMMON-SUBSTRATE SEMICONDUCTOR DEVICES HAVING NANOWIRES OR SEMICOND...

EPITAXIAL WAFER AND A METHOD OF MANUFACTURING THEREOF

COMMON-SUBSTRATE SEMICONDUCTOR DEVICES HAVING NANOWIRES OR SEMICOND...

STACKING FAULT AND TWIN BLOCKING BARRIER FOR INTEGRATING III-V ON SI

HIGH HOLE MOBILITY P-CHANNEL GE TRANSISTOR STRUCTURE ON SI SUBSTRATE

Back gate doping for SOI substrates

Group III-V devices with delta-doped layer under channel region

Methods of forming buffer layer architecture on silicon and structu...

Buffer layers for device isolation of devices grown on silicon

DISLOCATION REMOVAL FROM A GROUP III-V FILM GROWN ON A SEMICONDUCTO...

Method for manufacturing a silicon-on-insulator (SOI) wafer with an...

VERTICAL SEMICONDUCTOR WAFER CARRIER

High Hole Mobility P-Channel Ge Transistor Structure on Si Substrate

Ultra-thin oxide bonding for S1 to S1 dual orientation bonding

Dual crystal orientation circuit devices on the same substrate

Dislocation-free InSb quantum well structure on Si using novel buff...

Buffer layers for device isolation of devices grown on silicon

Stacking fault and twin blocking barrier for integrating III-V on Si

Depositing polar materials on non-polar semiconductor substrates

Insulation layer for silicon-on-insulator wafer

Methods and apparatuses for manufacturing ultra thin device layers...

Methods of vertically stacking wafers using porous silicon

Method for manufacturing a silicon-on-Insulator (SOI) wafer with an...

Transistors with increased mobility in the channel zone and method...

Semiconductor wafers with non-standard crystal orientations and met...

Complete device layer transfer without edge exclusion via direct wa...

Devices and methods employing high thermal conductivity heat dissip...

Methods and apparatuses for manufacturing ultra thin device layers...