Philip J. Cacharelis

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Menlo Park, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Fabrication of semiconductor structure having two levels of buried...
- Patent number 5,899,714
- Issue date May 4, 1999
- National Semiconductor Corporation
- Douglas R. Farrenkopf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory transistor having underlapped floating gate
- Patent number 5,894,147
- Issue date Apr 13, 1999
- National Semiconductor Corporation
- Philip John Cacharelis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor structure having two levels of buried regions
- Patent number 5,889,315
- Issue date Mar 30, 1999
- National Semiconductor Corporation
- Douglas R. Farrenkopf
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating integrated circuit chip containing EEPROM and...
- Patent number 5,591,658
- Issue date Jan 7, 1997
- National Semiconductor Corporation
- Philip J. Cacharelis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabrication of integrated circuit chip containing EEPROM...
- Patent number 5,550,072
- Issue date Aug 27, 1996
- National Semiconductor Corporation
- Philip J. Cacharelis
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making a non-volatile memory cell utilizing polycrystalli...
- Patent number 5,108,939
- Issue date Apr 28, 1992
- National Semiconductor Corp.
- Martin H. Manley
- H01 - BASIC ELECTRIC ELEMENTS